| Line 17... |
Line 17... |
######################
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######################
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# soc_generate_verilog
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# soc_generate_verilog
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#####################
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#####################
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sub soc_generate_verilog{
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sub soc_generate_verilog{
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my ($soc)= @_;
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my ($soc,$sw_path)= @_;
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my $soc_name=$soc->object_get_attribute('soc_name');
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my $soc_name=$soc->object_get_attribute('soc_name');
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#my $top_ip=ip_gen->ip_gen_new();
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#my $top_ip=ip_gen->ip_gen_new();
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my $top_ip=ip_gen->top_gen_new();
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my $top_ip=ip_gen->top_gen_new();
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if(!defined $soc_name){$soc_name='soc'};
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if(!defined $soc_name){$soc_name='soc'};
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my @instances=$soc->soc_get_all_instances();
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my @instances=$soc->soc_get_all_instances();
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my $io_sim_v;
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my $io_sim_v;
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my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
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my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
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$core_id= 0 if(!defined $core_id);
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$core_id= 0 if(!defined $core_id);
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my $param_as_in_v="\tparameter\tCORE_ID=$core_id";
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my $param_as_in_v="\tparameter\tCORE_ID=$core_id,
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\tparameter\tSW_LOC=\"$sw_path\"";
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my $param_pass_v="\t.CORE_ID(CORE_ID)";
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my $param_pass_v="\t.CORE_ID(CORE_ID),\n\t.SW_LOC(SW_LOC)";
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my $body_v;
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my $body_v;
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my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all);
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my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all);
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my $wires=soc->new_wires();
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my $wires=soc->new_wires();
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my $intfc=interface->interface_new();
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my $intfc=interface->interface_new();
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| Line 82... |
Line 83... |
add_text_to_string(\$soc_v,$sockets_assign_v_all);
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add_text_to_string(\$soc_v,$sockets_assign_v_all);
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add_text_to_string(\$soc_v,$addr_map);
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add_text_to_string(\$soc_v,$addr_map);
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add_text_to_string(\$soc_v,"endmodule\n\n");
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add_text_to_string(\$soc_v,"endmodule\n\n");
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$soc->soc_add_top($top_ip);
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$soc->object_add_attribute('top_ip',undef,$top_ip);
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#print @assigned_wires;
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#print @assigned_wires;
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#generate topmodule
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#generate topmodule
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my $top_v = (defined $param_as_in_v )? "module ${soc_name}_top #(\n $param_as_in_v\n)(\n$io_sim_v\n);\n": "module ${soc_name}_top (\n $io_sim_v\n);\n";
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my $top_v = (defined $param_as_in_v )? "module ${soc_name}_top #(\n $param_as_in_v\n)(\n$io_sim_v\n);\n": "module ${soc_name}_top (\n $io_sim_v\n);\n";
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my $ins= gen_soc_instance_v($soc,$soc_name,$param_pass_v);
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my $ins= gen_soc_instance_v($soc,$soc_name,$param_pass_v);
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add_text_to_string(\$top_v,$functions_all);
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add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
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add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
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add_text_to_string(\$top_v,$ins);
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add_text_to_string(\$top_v,$ins);
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my ($readme,$prog)=gen_system_info($soc,$param_as_in_v);
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my ($readme,$prog)=gen_system_info($soc,$param_as_in_v);
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return ("$soc_v",$top_v,$readme,$prog);
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return ("$soc_v",$top_v,$readme,$prog);
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| Line 726... |
Line 727... |
my $v=$soc->soc_get_module_param_value($instance_id,$JTAG_INDEX);
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my $v=$soc->soc_get_module_param_value($instance_id,$JTAG_INDEX);
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$JTAG_INDEX = $v if (defined $v);
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$JTAG_INDEX = $v if (defined $v);
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$v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
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$v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
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$JTAG_INDEX = $v if (defined $v);
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$JTAG_INDEX = $v if (defined $v);
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my $BINFILE=$soc->soc_get_module_param_value($instance_id,'INIT_FILE_NAME');
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my $BINFILE=$soc->soc_get_module_param_value($instance_id,'JTAG_MEM_FILE');
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($BINFILE)=$BINFILE=~ /"([^"]*)"/ if(defined $BINFILE);
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($BINFILE)=$BINFILE=~ /"([^"]*)"/ if(defined $BINFILE);
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$BINFILE=(defined $BINFILE) ? $BINFILE.'.bin' : 'ram0.bin';
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$BINFILE=(defined $BINFILE) ? $BINFILE.'.bin' : 'ram0.bin';
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my $OFSSET="0x00000000";
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my $OFSSET="0x00000000";
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my $end=((1<<$aw)*($dw/8))-1;
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my $end=((1<<$aw)*($dw/8))-1;
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