OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [main_comp.v] - Diff between revs 48 and 54

Show entire file | Details | Blame | View Log

Rev 48 Rev 54
Line 25... Line 25... 
**      Description:
 
**      Description:
 
**      This file contains several general RTL modules such as
 
**      This file contains several general RTL modules such as
 
**      different types of multiplexors, converters and counters ...
 
**      different types of multiplexors, converters and counters ...
 
**
 
**
 
**************************************************************/
 
**************************************************************/
 
 
 
`include "pronoc_def.v"
 
 
 
 
 
 
 
module pronoc_register
 
 
 
       #(
 
 
 
        parameter W=1,
 
 
 
        parameter  RESET_TO={W{1'b0}}
 
 
 
 
 
 
 
        )(
 
 
 
            input [W-1:0] in,
 
 
 
            input reset,
 
 
 
            input clk,
 
 
 
            output [W-1:0] out
 
 
 
        );
 
 
 
 
 
 
 
    pronoc_register_reset_init #(
 
 
 
        .W(W)
 
 
 
    )reg1(
 
 
 
        .in(in),
 
 
 
        .reset(reset),
 
 
 
        .clk(clk),
 
 
 
        .out(out),
 
 
 
        .reset_to(RESET_TO[W-1 : 0])
 
 
 
    );
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
module pronoc_register_reset_init
 
 
 
        #(
 
 
 
        parameter W=1
 
 
 
        )(
 
 
 
        input [W-1:0] in,
 
 
 
        input reset,
 
 
 
        input clk,
 
 
 
        output reg [W-1:0] out,
 
 
 
        input [W-1 : 0] reset_to
 
 
 
        );
 
 
 
 
 
 
 
 
 
 
 
        always @ (`pronoc_clk_reset_edge )begin
 
 
 
            if(`pronoc_reset)   out<=reset_to;
 
 
 
            else        out<=in;
 
 
 
        end
 
 
 
 
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
module pronoc_register_reset_init_ld_en
 
 
 
        #(
 
 
 
        parameter W=1
 
 
 
        )(
 
 
 
        input [W-1:0] in,
 
 
 
        input reset,
 
 
 
        input clk,
 
 
 
        input ld,
 
 
 
        output reg [W-1:0] out,
 
 
 
        input [W-1 : 0] reset_to
 
 
 
        );
 
 
 
 
 
 
 
        always @ (`pronoc_clk_reset_edge )begin
 
 
 
            if(`pronoc_reset)   out<=reset_to;
 
 
 
            else  if(ld)      out<=in;
 
 
 
        end
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
module pronoc_register_ld_en
 
 
 
       #(
 
 
 
        parameter W=1,
 
 
 
        parameter  RESET_TO={W{1'b0}}
 
 
 
 
 
 
 
        )(
 
 
 
            input [W-1:0] in,
 
 
 
            input reset,
 
 
 
            input clk,
 
 
 
            input ld,
 
 
 
            output [W-1:0] out
 
 
 
        );
 
 
 
 
 
 
 
    pronoc_register_reset_init_ld_en  #(
 
 
 
        .W(W)
 
 
 
    )reg1(
 
 
 
        .in(in),
 
 
 
        .reset(reset),
 
 
 
        .clk(clk),
 
 
 
        .ld(ld),
 
 
 
        .out(out),
 
 
 
        .reset_to(RESET_TO[W-1 : 0])
 
 
 
    );
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
/*********************************
 
/*********************************
 
 
 
 
 
 
 
 
Line 478... Line 564... 
    check_single_bit_assertation
 
    check_single_bit_assertation
 
 
 
 
 
*******************************/
 
*******************************/
 
 
 
 
 
 
 
 
 
module check_single_bit_assertation #(
 
module is_onehot0 #(
 
    parameter IN_WIDTH =2
 
    parameter IN_WIDTH =2
 
 
 
 
 
    )
 
    )
 
    (
 
    (
 
    input   [IN_WIDTH-1         :   0]  in,
 
    input   [IN_WIDTH-1         :   0]  in,
Line 503... Line 589... 
 
 
 
 
    localparam OUT_WIDTH = log2(IN_WIDTH+1);
 
    localparam OUT_WIDTH = log2(IN_WIDTH+1);
 
 
 
 
 
    wire [OUT_WIDTH-1   :   0]  sum;
 
    wire [OUT_WIDTH-1   :   0]  sum;
 
 
 
 
 
    parallel_counter #(
 
 
 
        .IN_WIDTH (IN_WIDTH)
 
    accumulator #(
 
    )counter
 
        .INw(IN_WIDTH),
 
 
 
        .OUTw(OUT_WIDTH),
 
 
 
        .NUM(IN_WIDTH)
 
 
 
    )
 
 
 
    accum
 
    (
 
    (
 
        .in(in),
 
        .in_all(in),
 
        .out(sum)
 
        .out(sum)
 
    );
 
    );
 
 
 
 
 
 
 
 
 
 
 
    /*
 
 
 
    parallel_counter #(
 
 
 
        .IN_WIDTH (IN_WIDTH)
 
 
 
    )counter
 
 
 
    (
 
 
 
        .in(in),
 
 
 
        .out(sum)
 
 
 
    );
 
 
 
    */
 
 
 
 
 
    assign result = (sum <=1)? 1'b1: 1'b0;
 
    assign result = (sum <=1)? 1'b1: 1'b0;
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
Line 922... Line 1023... 
 
 
 
 
endgenerate
 
endgenerate
 
 
 
 
 
    reg [2:0] counter;
 
    reg [2:0] counter;
 
    assign cnt_increase=(counter==3'd0);
 
    assign cnt_increase=(counter==3'd0);
 
    always @(posedge clk or posedge reset) begin
 
    always @ (`pronoc_clk_reset_edge )begin
 
        if(reset) begin
 
        if(`pronoc_reset)  begin
 
            start_o_reg <= {NC{1'b0}};
 
            start_o_reg <= {NC{1'b0}};
 
            start_i_reg <= 1'b0;
 
            start_i_reg <= 1'b0;
 
            counter <= 3'd0;
 
            counter <= 3'd0;
 
        end else begin
 
        end else begin
 
            counter <= counter+3'd1;
 
            counter <= counter+3'd1;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.