| Line 200... |
Line 200... |
output [PPSw-1 : 0] port_pre_sel;
|
output [PPSw-1 : 0] port_pre_sel;
|
|
|
|
|
|
|
reg [BVw-1 : 0] credit_per_port_next [P_1-1 : 0];
|
reg [BVw-1 : 0] credit_per_port_next [P_1-1 : 0];
|
reg [BVw-1 : 0] credit_per_port [P_1-1 : 0];
|
wire [BVw-1 : 0] credit_per_port [P_1-1 : 0];
|
wire [P_1-1 : 0] credit_increased_per_port;
|
wire [P_1-1 : 0] credit_increased_per_port;
|
wire [P_1-1 : 0] credit_decreased_per_port;
|
wire [P_1-1 : 0] credit_decreased_per_port;
|
wire [P_1-1 : 0] conjestion_cmp;
|
wire [P_1-1 : 0] conjestion_cmp;
|
|
|
|
|
| Line 226... |
Line 226... |
end
|
end
|
end//for
|
end//for
|
end//always
|
end//always
|
|
|
for(i=0; i<P_1; i=i+1'b1) begin :blk2
|
for(i=0; i<P_1; i=i+1'b1) begin :blk2
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
pronoc_register #(
|
`else
|
.W(BVw),
|
always @ (posedge clk or posedge reset)begin
|
.RESET_TO(C_INT)
|
`endif
|
) reg1 (
|
|
.in(credit_per_port_next[i]),
|
if(reset) begin
|
.reset(reset),
|
credit_per_port[i] <= C_INT;
|
.clk(clk),
|
end else begin
|
.out(credit_per_port[i])
|
credit_per_port[i] <= credit_per_port_next[i];
|
);
|
end
|
|
end//for
|
end//for
|
end
|
|
|
|
endgenerate//always
|
endgenerate
|
|
|
/*******************
|
/*******************
|
pre-sel[xy]
|
pre-sel[xy]
|
y
|
y
|
1 | 3
|
1 | 3
|
| Line 344... |
Line 343... |
|
|
|
|
|
|
|
|
// assign port_pre_sel = conjestion_cmp;
|
// assign port_pre_sel = conjestion_cmp;
|
register #(.W(PPSw)) reg1 (.in(conjestion_cmp ), .reset(reset), .clk(clk), .out(port_pre_sel));
|
pronoc_register #(.W(PPSw)) reg1 (.in(conjestion_cmp ), .reset(reset), .clk(clk), .out(port_pre_sel));
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
| Line 673... |
Line 672... |
output [CONG_ALw-1 : 0] congestion_out_all;
|
output [CONG_ALw-1 : 0] congestion_out_all;
|
input clk,reset;
|
input clk,reset;
|
|
|
wire [IVC_CNTw-1 : 0] ivc_req_num;
|
wire [IVC_CNTw-1 : 0] ivc_req_num;
|
reg [CONGw-1 : 0] congestion_out ;
|
reg [CONGw-1 : 0] congestion_out ;
|
reg [PV-1 : 0] ivc_request_not_granted;
|
wire [PV-1 : 0] ivc_request_not_granted;
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
pronoc_register #(
|
`else
|
.W(PV)
|
always @ (posedge clk or posedge reset)begin
|
) reg1 (
|
`endif
|
.in(ivc_request_all & ~ivc_num_getting_sw_grant),
|
if(reset) begin
|
.reset(reset),
|
ivc_request_not_granted <= 0;
|
.clk(clk),
|
end else begin
|
.out(ivc_request_not_granted)
|
ivc_request_not_granted <= ivc_request_all & ~(ivc_num_getting_sw_grant);
|
);
|
end//reset
|
|
end //always
|
|
|
|
|
|
accumulator #(
|
accumulator #(
|
.INw(PV),
|
.INw(PV),
|
.OUTw(IVC_CNTw),
|
.OUTw(IVC_CNTw),
|
| Line 1179... |
Line 1176... |
assign counter_in[NORTH] ={ovc_not_avb[EAST] ,ovc_not_avb[WEST] ,ovc_not_avb[SOUTH]};
|
assign counter_in[NORTH] ={ovc_not_avb[EAST] ,ovc_not_avb[WEST] ,ovc_not_avb[SOUTH]};
|
assign counter_in[WEST] ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[SOUTH]};
|
assign counter_in[WEST] ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[SOUTH]};
|
assign counter_in[SOUTH] ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[WEST]};
|
assign counter_in[SOUTH] ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[WEST]};
|
|
|
// counting not granted requests
|
// counting not granted requests
|
reg [PV-1 : 0] ivc_request_not_granted;
|
wire [PV-1 : 0] ivc_request_not_granted;
|
wire [V-1 : 0] ivc_not_grnt [P_1-1 : 0];
|
wire [V-1 : 0] ivc_not_grnt [P_1-1 : 0];
|
wire [CNT_Vw-1 : 0] ivc_not_grnt_num [P_1-1 : 0];
|
wire [CNT_Vw-1 : 0] ivc_not_grnt_num [P_1-1 : 0];
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset) begin
|
|
ivc_request_not_granted <= 0;
|
|
end else begin
|
|
ivc_request_not_granted <= ivc_request_all & ~(ivc_num_getting_sw_grant);
|
|
end//reset
|
|
end //always
|
|
|
|
|
pronoc_register #(
|
|
.W(PV)
|
|
) reg1 (
|
|
.in(ivc_request_all & ~ivc_num_getting_sw_grant),
|
|
.reset(reset),
|
|
.clk(clk),
|
|
.out(ivc_request_not_granted)
|
|
);
|
|
|
assign {ivc_not_grnt[SOUTH], ivc_not_grnt[WEST], ivc_not_grnt[NORTH],ivc_not_grnt[EAST]}= ivc_request_not_granted[PV-1 : V];
|
assign {ivc_not_grnt[SOUTH], ivc_not_grnt[WEST], ivc_not_grnt[NORTH],ivc_not_grnt[EAST]}= ivc_request_not_granted[PV-1 : V];
|
|
|
|
|
|
|
| Line 1455... |
Line 1449... |
CONG_ALw = CONGw* P; // congestion width per router;;
|
CONG_ALw = CONGw* P; // congestion width per router;;
|
|
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PV-1 : 0] ivc_request_all;
|
input [PV-1 : 0] ivc_request_all;
|
input [PV-1 : 0] ivc_num_getting_sw_grant;
|
input [PV-1 : 0] ivc_num_getting_sw_grant;
|
output reg [CONG_ALw-1 : 0] congestion_out_all;
|
output [CONG_ALw-1 : 0] congestion_out_all;
|
input clk,reset;
|
input clk,reset;
|
|
|
wire [CONG_ALw-1 : 0] congestion_out_all_next;
|
wire [CONG_ALw-1 : 0] congestion_out_all_next;
|
generate
|
generate
|
if(ROUTE_TYPE != "DETERMINISTIC") begin :adpt
|
if(ROUTE_TYPE != "DETERMINISTIC") begin :adpt
|
| Line 1568... |
Line 1562... |
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset)begin
|
|
congestion_out_all <= {CONG_ALw{1'b0}};
|
|
end else begin
|
|
congestion_out_all <= congestion_out_all_next;
|
|
|
|
end
|
pronoc_register #(
|
end //always
|
.W(CONG_ALw)
|
|
) reg1 (
|
|
.in(congestion_out_all_next),
|
|
.reset(reset),
|
|
.clk(clk),
|
|
.out(congestion_out_all)
|
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
| Line 1626... |
Line 1617... |
|
|
input [PV-1 : 0] ivc_num_getting_sw_grant, ivc_request_all;
|
input [PV-1 : 0] ivc_num_getting_sw_grant, ivc_request_all;
|
input reset,clk;
|
input reset,clk;
|
output detect;
|
output detect;
|
|
|
reg [CNTw-1 : 0] counter [V-1 : 0];
|
wire [CNTw-1 : 0] counter [V-1 : 0];
|
|
reg [CNTw-1 : 0] counter_next [V-1 : 0];
|
wire [P-1 : 0] counter_rst_gen [V-1 : 0];
|
wire [P-1 : 0] counter_rst_gen [V-1 : 0];
|
wire [P-1 : 0] counter_en_gen [V-1 : 0];
|
wire [P-1 : 0] counter_en_gen [V-1 : 0];
|
wire [V-1 : 0] counter_rst,counter_en,detect_gen;
|
wire [V-1 : 0] counter_rst,counter_en,detect_gen;
|
reg [PV-1 : 0] ivc_num_getting_sw_grant_reg;
|
wire [PV-1 : 0] ivc_num_getting_sw_grant_reg;
|
|
|
|
|
|
pronoc_register #(
|
|
.W(PV)
|
|
) reg1 (
|
|
.in(ivc_num_getting_sw_grant),
|
|
.reset(reset),
|
|
.clk(clk),
|
|
.out(ivc_num_getting_sw_grant_reg)
|
|
);
|
|
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
|
|
if(reset) begin
|
|
ivc_num_getting_sw_grant_reg <= {PV{1'b0}};
|
|
end else begin
|
|
ivc_num_getting_sw_grant_reg <= ivc_num_getting_sw_grant;
|
|
end
|
|
end
|
|
|
|
//seperate all same virtual chanels requests
|
//seperate all same virtual chanels requests
|
genvar i,j;
|
genvar i,j;
|
generate
|
generate
|
for (i=0;i<V;i=i+1)begin:v_loop
|
for (i=0;i<V;i=i+1)begin:v_loop
|
| Line 1657... |
Line 1648... |
end//j
|
end//j
|
//sum all signals belong to the same VC
|
//sum all signals belong to the same VC
|
assign counter_rst[i] =|counter_rst_gen[i];
|
assign counter_rst[i] =|counter_rst_gen[i];
|
assign counter_en[i] =|counter_en_gen [i];
|
assign counter_en[i] =|counter_en_gen [i];
|
// generate the counter
|
// generate the counter
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset) begin
|
|
counter[i]<={CNTw{1'b0}};
|
|
end else begin
|
|
if(counter_rst[i]) counter[i]<={CNTw{1'b0}};
|
|
else if(counter_en[i]) counter[i]<=counter[i]+1'b1;
|
|
end//reset
|
|
end//always
|
|
// check counters value to detect deadlock
|
|
assign detect_gen[i]= (counter[i]== MAX_CLK-1);
|
|
|
|
end//i
|
|
|
|
assign detect=|detect_gen;
|
always @ (*) begin
|
|
counter_next[i] = counter[i];
|
|
if(counter_rst[i]) counter_next[i] = {CNTw{1'b0}};
|
|
else if(counter_en[i]) counter_next[i] = counter[i]+1'b1;
|
|
end//always
|
|
|
|
|
|
pronoc_register #(
|
|
.W(CNTw)
|
|
) reg2 (
|
|
.in(counter_next[i]),
|
|
.reset(reset),
|
|
.clk(clk),
|
|
.out(counter[i])
|
|
);
|
|
|
|
// check counters value to detect deadlock
|
|
assign detect_gen[i]= (counter[i]== MAX_CLK-1);
|
|
|
|
end//i
|
endgenerate
|
endgenerate
|
|
|
|
assign detect=|detect_gen;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
