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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [fattree_route.v] - Diff between revs 48 and 54

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Rev 48 Rev 54
Line 63... Line 63... 
    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
 
    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
 
    wire  [Kw-1 :0]  current_node_dest_port;
 
    wire  [Kw-1 :0]  current_node_dest_port;
 
 
 
 
 
    wire [L-1 : 0] parrents_node_missmatch;
 
    wire [L-1 : 0] parrents_node_missmatch;
 
 
 
 
 
    reg [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
 
    wire [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
 
 
 
 
 
 
 
     pronoc_register #(
 
 
 
           .W(K),
 
 
 
           .RESET_TO(1)
 
 
 
      ) reg1 (
 
 
 
           .in({counter[0],counter[K-1:1]}),
 
 
 
           .reset(reset),
 
 
 
           .clk(clk),
 
 
 
           .out(counter)
 
 
 
      );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`ifdef SYNC_RESET_MODE
 
 
 
    always @ (posedge clk )begin
 
 
 
`else
 
 
 
    always @ (posedge clk or posedge reset)begin
 
 
 
`endif
 
 
 
        if(reset) begin
 
 
 
            counter <= 1;
 
 
 
        end
 
 
 
        else begin
 
 
 
            counter <= {counter[0],counter[K-1:1]};
 
 
 
        end
 
 
 
    end
 
 
 
 
 
 
 
    assign current_addr [0]={Kw{1'b0}};
 
    assign current_addr [0]={Kw{1'b0}};
 
    assign parrent_dest_addr [0]={Kw{1'b0}};
 
    assign parrent_dest_addr [0]={Kw{1'b0}};
 
 
 
 
 
    genvar i;
 
    genvar i;
Line 179... Line 180... 
    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
 
    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
 
    wire  [Kw-1 :0]  current_node_dest_port;
 
    wire  [Kw-1 :0]  current_node_dest_port;
 
 
 
 
 
    wire [L-1 : 0] parrents_node_missmatch;
 
    wire [L-1 : 0] parrents_node_missmatch;
 
 
 
 
 
    reg [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
 
    wire [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
 
 
 
 
 
`ifdef SYNC_RESET_MODE
 
     pronoc_register #(
 
    always @ (posedge clk )begin
 
           .W(K),
 
`else
 
           .RESET_TO(1)
 
    always @ (posedge clk or posedge reset)begin
 
      ) reg1 (
 
`endif
 
           .in({counter[0],counter[K-1:1]}),
 
        if(reset) begin
 
           .reset(reset),
 
            counter <= 1;
 
           .clk(clk),
 
        end
 
           .out(counter)
 
        else begin
 
      );
 
            counter <= {counter[0],counter[K-1:1]};
 
 
 
        end
 
 
 
    end
 
 
 
 
 
 
 
    assign current_addr [0]={Kw{1'b0}};
 
    assign current_addr [0]={Kw{1'b0}};
 
    assign parrent_dest_addr [0]={Kw{1'b0}};
 
    assign parrent_dest_addr [0]={Kw{1'b0}};
 
 
 
 
 
    genvar i;
 
    genvar i;
Line 296... Line 294... 
    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
 
    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
 
    wire  [Kw-1 :0]  current_node_dest_port;
 
    wire  [Kw-1 :0]  current_node_dest_port;
 
 
 
 
 
    wire [L-1 : 0] parrents_node_missmatch;
 
    wire [L-1 : 0] parrents_node_missmatch;
 
 
 
 
 
    reg [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
 
    wire  [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
 
 
 
 
 
`ifdef SYNC_RESET_MODE
 
     pronoc_register #(
 
    always @ (posedge clk )begin
 
           .W(K),
 
`else
 
           .RESET_TO(1)
 
    always @ (posedge clk or posedge reset)begin
 
      ) reg1 (
 
`endif
 
           .in({counter[0],counter[K-1:1]}),
 
        if(reset) begin
 
           .reset(reset),
 
            counter <= 1;
 
           .clk(clk),
 
        end
 
           .out(counter)
 
        else begin
 
      );
 
            counter <= {counter[0],counter[K-1:1]};
 
 
 
        end
 
 
 
    end
 
 
 
 
 
 
 
    assign current_addr [0]={Kw{1'b0}};
 
    assign current_addr [0]={Kw{1'b0}};
 
    assign parrent_dest_addr [0]={Kw{1'b0}};
 
    assign parrent_dest_addr [0]={Kw{1'b0}};
 
 
 
 
 
    genvar i;
 
    genvar i;
Line 524... Line 519... 
    input  [PLKw-1 : 0]  neighbors_rx;
 
    input  [PLKw-1 : 0]  neighbors_rx;
 
    input  [PLw-1 : 0]  neighbors_ry;
 
    input  [PLw-1 : 0]  neighbors_ry;
 
    output [K: 0]    lkdestport_encoded;
 
    output [K: 0]    lkdestport_encoded;
 
    input                   reset,clk;
 
    input                   reset,clk;
 
 
 
 
 
    reg  [K :0]    destport_encoded_delayed;
 
    wire  [K :0]    destport_encoded_delayed;
 
    reg  [LKw-1 :0]    dest_addr_encoded_delayed;
 
    wire  [LKw-1 :0]    dest_addr_encoded_delayed;
 
 
 
 
 
     fattree_deterministic_look_ahead_routing #(
 
     fattree_deterministic_look_ahead_routing #(
 
        .P(P),
 
        .P(P),
 
        .ROUTE_NAME(ROUTE_NAME),
 
        .ROUTE_NAME(ROUTE_NAME),
 
        .K(K),
 
        .K(K),
Line 545... Line 540... 
        .neighbors_ry(neighbors_ry),
 
        .neighbors_ry(neighbors_ry),
 
        .lkdestport_encoded(lkdestport_encoded)
 
        .lkdestport_encoded(lkdestport_encoded)
 
     );
 
     );
 
 
 
 
 
 
 
 
 
`ifdef SYNC_RESET_MODE
 
      pronoc_register #(
 
    always @ (posedge clk )begin
 
           .W(K+1)
 
`else
 
      ) reg1 (
 
    always @ (posedge clk or posedge reset)begin
 
           .in(destport_encoded),
 
`endif
 
           .reset(reset),
 
        if(reset)begin
 
           .clk(clk),
 
            destport_encoded_delayed <= {(K+1){1'b0}};
 
           .out(destport_encoded_delayed)
 
            dest_addr_encoded_delayed<= {LKw{1'b0}};
 
      );
 
        end else begin
 
 
 
            destport_encoded_delayed<=destport_encoded;
 
       pronoc_register #(
 
            dest_addr_encoded_delayed<=dest_addr_encoded;
 
           .W(LKw)
 
        end//else reset
 
      ) reg2 (
 
    end//always
 
           .in(dest_addr_encoded),
 
 
 
           .reset(reset),
 
 
 
           .clk(clk),
 
 
 
           .out(dest_addr_encoded_delayed)
 
 
 
      );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
Line 1114... Line 1117... 
            assign dest_port_out= destport_masked [P_1-1  :   0 ];
 
            assign dest_port_out= destport_masked [P_1-1  :   0 ];
 
        end
 
        end
 
        endgenerate
 
        endgenerate
 
 endmodule
 
 endmodule
 
 
 
 
 
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