| Line 67... |
Line 67... |
output [VCw-1 : 0] class_all;
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output [VCw-1 : 0] class_all;
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// output [VDSTPw-1 :0 ] dest_port_encoded_all;
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// output [VDSTPw-1 :0 ] dest_port_encoded_all;
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// input [V-1 :0] ssa_rd;
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// input [V-1 :0] ssa_rd;
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wire [Fw-1 :0] dout_all [V-1 : 0]; // Data out
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wire [Fw-1 :0] dout_all [V-1 : 0]; // Data out
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reg [VCw-1 : 0] class_vc [V-1 : 0];
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wire [VCw-1 : 0] class_vc [V-1 : 0];
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reg [REGFw-1 : 0] flit_regs [V-1 : 0]; // a register array save the head of each quque
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reg [VCw-1 : 0] class_vc_next [V-1 : 0];
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wire [REGFw-1 : 0] flit_regs [V-1 : 0]; // a register array save the head of each quque
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reg [REGFw-1 : 0] flit_regs_next [V-1 : 0];
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reg [V-1 : 0] valid,valid_next; // if valid is asseted it shows the VC queue has a flit waiting to be sent
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reg [V-1 : 0] valid,valid_next; // if valid is asseted it shows the VC queue has a flit waiting to be sent
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wire [Fw-1 : 0] bram_dout;
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wire [Fw-1 : 0] bram_dout;
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wire [V-1 : 0] bram_not_empty;
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wire [V-1 : 0] bram_not_empty;
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wire bram_wr_en;
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wire bram_wr_en;
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| Line 129... |
Line 131... |
always @(posedge clk) pass_din_to_flit_reg_delaied<=pass_din_to_flit_reg;
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always @(posedge clk) pass_din_to_flit_reg_delaied<=pass_din_to_flit_reg;
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assign dout = dout_all[vc_num_rd_bin_delaied];
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assign dout = dout_all[vc_num_rd_bin_delaied];
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flit_buffer #(
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flit_buffer #(
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.V(V),
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.B(B),
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.B(B),
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.PCK_TYPE(PCK_TYPE),
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.Fw(Fw),
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.DEBUG_EN(DEBUG_EN),
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.SSA_EN("NO")// should be "NO" even if SSA is enabled
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.SSA_EN("NO")// should be "NO" even if SSA is enabled
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)
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)
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flit_buffer
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flit_buffer
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(
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(
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.din(din),
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.din(din),
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| Line 149... |
Line 147... |
.rd_en(bram_rd_en),
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.rd_en(bram_rd_en),
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.dout(bram_dout),
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.dout(bram_dout),
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.vc_not_empty(bram_not_empty),
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.vc_not_empty(bram_not_empty),
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.ssa_rd({V{1'b0}})
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.ssa_rd({V{1'b0}}),
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.multiple_dest(),
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.sub_rd_ptr_ld(),
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.flit_is_tail()
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);
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);
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(reset) begin
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if(reset) begin
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| Line 199... |
Line 202... |
// assign dout_all[(i+1)*Fw-1 : i*Fw] = {flit_regs [i][REGFw-1: REGFw-2],i[V-1:0] ,flit_regs[i][Fpay-1:0]};
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// assign dout_all[(i+1)*Fw-1 : i*Fw] = {flit_regs [i][REGFw-1: REGFw-2],i[V-1:0] ,flit_regs[i][Fpay-1:0]};
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assign dout_all[i] = {flit_regs [i][REGFw-1: REGFw-2],i[V-1:0] ,flit_regs[i][Fpay-1:0]};
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assign dout_all[i] = {flit_regs [i][REGFw-1: REGFw-2],i[V-1:0] ,flit_regs[i][Fpay-1:0]};
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assign class_all[(i+1)*Cw-1 : i*Cw] = class_vc[i];
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assign class_all[(i+1)*Cw-1 : i*Cw] = class_vc[i];
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pronoc_register #(
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.W(REGFw)
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) reg1 (
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.in(flit_regs_next[i]),
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.reset(reset),
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.clk(clk),
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.out(flit_regs[i])
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);
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pronoc_register #(
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.W(Cw)
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) reg2 (
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.in(class_vc_next[i]),
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.reset(reset),
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.clk(clk),
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.out(class_vc[i])
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);
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`ifdef SYNC_RESET_MODE
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always @ (*)begin
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always @ (posedge clk )begin
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flit_regs_next[i] = flit_regs[i];
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`else
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class_vc_next[i] = class_vc[i];
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always @ (posedge clk or posedge reset)begin
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if(pass_din_to_flit_reg_delaied[i]) flit_regs_next[i] = {din[Fw-1:Fw-2],din_reg[Fpay-1:0]} ;
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`endif
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if(bram_out_is_valid_delaied[i]) flit_regs_next[i] = {bram_dout[Fw-1:Fw-2],bram_dout[Fpay-1:0]};
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if(reset)begin
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if(flit_reg_wr_en[i] & flit_reg_mux_out[REGFw-1] ) class_vc_next[i] = class_i;// writing header flit
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flit_regs[i]<= {REGFw{1'b0}};
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class_vc[i]<= {Cw{1'b0}};
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// dest_port_encoded_vc[i]<={DSTPw{1'b0}};
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end
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else begin //1 :din, 0: bram
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// if(pass_din_to_flit_reg_delaied[i] & (flit_reg_mux_sel_delay==1'b0)) $display("EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE");
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// if( bram_out_is_valid_delaied[i] & flit_reg_mux_sel_delay) $display("RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR");
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if(pass_din_to_flit_reg_delaied[i]) flit_regs[i] <= {din[Fw-1:Fw-2],din_reg[Fpay-1:0]} ;
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if(bram_out_is_valid_delaied[i]) flit_regs[i] <= {bram_dout[Fw-1:Fw-2],bram_dout[Fpay-1:0]};
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if(flit_reg_wr_en[i] & flit_reg_mux_out[REGFw-1] ) class_vc[i]<=class_i;// writing header flit
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// if(destport_clear[i]>0) dest_port_encoded_vc<= dest_port_encoded_vc & ~destport_clear[i];
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// else if(flit_reg_wr_en[i] & flit_reg_mux_out[REGFw-1] ) dest_port_encoded_vc <=destport_i;
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end
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end
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end
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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/*
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/*
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if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
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if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
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`ifdef SYNC_RESET_MODE
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always @ (`pronoc_clk_reset_edge )begin
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always @ (posedge clk )begin
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if(`pronoc_reset)begin
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`else
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always @ (posedge clk or posedge reset)begin
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`endif
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if(reset)begin
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end else begin
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end else begin
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dest_port_encoded_vc[i]<= destport_in_encoded;
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dest_port_encoded_vc[i]<= destport_in_encoded;
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end
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end
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end//always
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end//always
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