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`timescale 1ns / 1ps
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`include "pronoc_def.v"
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/**********************************************************************
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/**********************************************************************
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** File: header_flit.sv
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** File: header_flit.sv
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** Date:2017-07-11
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** Date:2017-07-11
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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output [Fw-1 : 0] flit_out;
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output [Fw-1 : 0] flit_out;
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input [Cw-1 : 0] class_in;
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input [Cw-1 : 0] class_in;
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input [EAw-1 : 0] dest_e_addr_in;
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input [DAw-1 : 0] dest_e_addr_in;
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input [EAw-1 : 0] src_e_addr_in;
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input [EAw-1 : 0] src_e_addr_in;
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input [V-1 : 0] vc_num_in;
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input [V-1 : 0] vc_num_in;
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input [WEIGHTw-1 : 0] weight_in;
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input [WEIGHTw-1 : 0] weight_in;
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input [DSTPw-1 : 0] destport_in;
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input [DSTPw-1 : 0] destport_in;
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input [BEw-1 : 0] be_in;
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input [BEw-1 : 0] be_in;
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input [Fw-1 : 0] flit_in;
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input [Fw-1 : 0] flit_in;
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input flit_in_wr;
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input flit_in_wr;
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output [EAw-1 : 0] src_e_addr_o;
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output [EAw-1 : 0] src_e_addr_o;
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output [EAw-1 : 0] dest_e_addr_o;
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output [DAw-1 : 0] dest_e_addr_o;
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output [DSTPw-1 : 0] destport_o;
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output [DSTPw-1 : 0] destport_o;
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output [Cw-1 : 0] class_o;
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output [Cw-1 : 0] class_o;
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output [W-1 : 0] weight_o;
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output [W-1 : 0] weight_o;
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output tail_flg_o;
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output tail_flg_o;
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output hdr_flg_o;
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output hdr_flg_o;
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localparam
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localparam
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VDSTPw = V * DSTPw,
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VDSTPw = V * DSTPw,
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VV = V * V;
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VV = V * V;
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localparam
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E_SRC_LSB =0, E_SRC_MSB = E_SRC_LSB + EAw-1,
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E_DST_LSB = E_SRC_MSB +1, E_DST_MSB = E_DST_LSB + EAw-1,
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DST_P_LSB = E_DST_MSB + 1, DST_P_MSB = DST_P_LSB + DSTPw-1;
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input [Fw-1 : 0] flit_in;
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input [Fw-1 : 0] flit_in;
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output reg [Fw-1 : 0] flit_out;
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output reg [Fw-1 : 0] flit_out;
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input [V-1 : 0] vc_num_in;
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input [V-1 : 0] vc_num_in;
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input [V-1 : 0] sel;
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input [V-1 : 0] sel;
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input any_ivc_sw_request_granted;
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input any_ivc_sw_request_granted;
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input [DSTPw-1 : 0] lk_dest_not_registered;
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input [DSTPw-1 : 0] lk_dest_not_registered;
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wire hdr_flag;
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wire hdr_flag;
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reg [V-1 : 0] vc_num_delayed;
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logic [V-1 : 0] vc_num_delayed;
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wire [V-1 : 0] ovc_num;
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wire [V-1 : 0] ovc_num;
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wire [DSTPw-1 : 0] lk_dest,dest_coded;
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wire [DSTPw-1 : 0] lk_dest,dest_coded;
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wire [DSTPw-1 : 0] lk_mux_out;
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wire [DSTPw-1 : 0] lk_mux_out;
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pronoc_register #(.W(V)) reg1 (.in(vc_num_in), .out(vc_num_delayed), .reset(reset), .clk(clk));
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`ifdef SYNC_RESET_MODE
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always @ (posedge clk )begin
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`else
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always @ (posedge clk or posedge reset)begin
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`endif
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if(reset) begin
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vc_num_delayed <= {V{1'b0}};
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//assigned_ovc_num_delayed <= {VV{1'b0}};
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end else begin
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vc_num_delayed<= vc_num_in;
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//assigned_ovc_num_delayed <=assigned_ovc_num;
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end
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end
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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assign hdr_flag = ( PCK_TYPE == "MULTI_FLIT")? flit_in[Fw-1]: 1'b1;
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assign hdr_flag = ( PCK_TYPE == "MULTI_FLIT")? flit_in[Fw-1]: 1'b1;
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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onehot_mux_1D #(
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onehot_mux_1D #(
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generate
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generate
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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if( SSA_EN == "YES" ) begin : predict // bypass the lk fifo when no ivc is granted
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if( SSA_EN == "YES" ) begin : predict // bypass the lk fifo when no ivc is granted
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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reg ivc_any_delayed;
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logic ivc_any_delayed;
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`ifdef SYNC_RESET_MODE
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pronoc_register #(.W(1)) reg2 (.in(any_ivc_sw_request_granted ), .out(ivc_any_delayed), .reset(reset), .clk(clk));
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always @ (posedge clk )begin
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`else
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always @ (posedge clk or posedge reset)begin
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`endif
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if(reset) begin
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ivc_any_delayed <= 1'b0;
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end else begin
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ivc_any_delayed <= any_ivc_sw_request_granted;
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end
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end
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assign lk_dest = (ivc_any_delayed == 1'b0)? lk_dest_not_registered : lk_mux_out;
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assign lk_dest = (ivc_any_delayed == 1'b0)? lk_dest_not_registered : lk_mux_out;
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end else begin : no_predict
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end else begin : no_predict
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assign lk_dest =lk_mux_out;
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assign lk_dest =lk_mux_out;
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