| Line 1... |
Line 1... |
`timescale 1ns/1ps
|
`include "pronoc_def.v"
|
|
|
/**********************************************************************
|
/**********************************************************************
|
** File: inout_ports.v
|
** File: inout_ports.v
|
**
|
**
|
** Copyright (C) 2014-2017 Alireza Monemi
|
** Copyright (C) 2014-2017 Alireza Monemi
|
**
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**
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| Line 65... |
Line 64... |
dest_port_all,
|
dest_port_all,
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ovc_is_assigned_all,
|
ovc_is_assigned_all,
|
ivc_request_all,
|
ivc_request_all,
|
assigned_ovc_not_full_all,
|
assigned_ovc_not_full_all,
|
masked_ovc_request_all,
|
masked_ovc_request_all,
|
pck_is_single_flit_all,
|
|
vc_weight_is_consumed_all,
|
vc_weight_is_consumed_all,
|
iport_weight_is_consumed_all,
|
iport_weight_is_consumed_all,
|
flit_is_tail_all,
|
flit_is_tail_all,
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|
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// to crossbar
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// to crossbar
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| Line 137... |
Line 135... |
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|
|
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// to vc/sw allocator
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// to vc/sw allocator
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output [PVP_1-1 : 0] dest_port_all;
|
output [PVP_1-1 : 0] dest_port_all;
|
output [PV-1 : 0] ovc_is_assigned_all;
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output [PV-1 : 0] ovc_is_assigned_all;
|
output [PV-1 : 0] pck_is_single_flit_all;
|
|
output [PV-1 : 0] ivc_request_all;
|
output [PV-1 : 0] ivc_request_all;
|
output [PV-1 : 0] assigned_ovc_not_full_all;
|
output [PV-1 : 0] assigned_ovc_not_full_all;
|
output [PVV-1: 0] masked_ovc_request_all;
|
output [PVV-1: 0] masked_ovc_request_all;
|
output [PV-1 : 0] flit_is_tail_all;
|
output [PV-1 : 0] flit_is_tail_all;
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|
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| Line 165... |
Line 162... |
input vsa_ctrl_t vsa_ctrl_in [P-1 : 0];
|
input vsa_ctrl_t vsa_ctrl_in [P-1 : 0];
|
input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
|
input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
|
output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
|
output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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|
|
|
|
wire [PVV-1 : 0] candidate_ovc_all;
|
|
wire [PVDSTPw-1 : 0] dest_port_encoded_all;
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|
|
|
|
|
wire [PPSw-1 : 0] port_pre_sel;
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wire [PPSw-1 : 0] port_pre_sel;
|
wire [PV-1 : 0] swap_port_presel;
|
wire [PV-1 : 0] swap_port_presel;
|
wire [PV-1 : 0] reset_ivc_all;
|
wire [PV-1 : 0] reset_ivc_all;
|
|
|
wire [PV-1 : 0] ovc_is_assigned_all;
|
|
wire [PVV-1 : 0] assigned_ovc_num_all;
|
|
|
|
wire [PV-1 : 0] sel;
|
wire [PV-1 : 0] sel;
|
wire [PV-1 : 0] ovc_avalable_all;
|
wire [PV-1 : 0] ovc_avalable_all;
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|
|
wire [PVDSTPw-1 : 0] destport_clear_all;// clear non preferable ports in adaptive routing
|
wire [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0]; // clear non preferable ports in adaptive routing
|
wire [PV-1 : 0] ivc_num_getting_sw_grant;
|
wire [PV-1 : 0] ivc_num_getting_sw_grant;
|
|
|
ssa_ctrl_t ssa_ctrl [P-1 : 0];
|
ssa_ctrl_t ssa_ctrl [P-1 : 0];
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|
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| Line 201... |
Line 193... |
.flit_in_all (flit_in_all),
|
.flit_in_all (flit_in_all),
|
.flit_in_wr_all (flit_in_wr_all),
|
.flit_in_wr_all (flit_in_wr_all),
|
.reset_ivc_all (reset_ivc_all),
|
.reset_ivc_all (reset_ivc_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.ivc_request_all (ivc_request_all),
|
.ivc_request_all (ivc_request_all),
|
.dest_port_encoded_all (dest_port_encoded_all),
|
|
.dest_port_all(dest_port_all),
|
.dest_port_all(dest_port_all),
|
.candidate_ovcs_all (candidate_ovc_all),
|
|
.flit_out_all (flit_out_all),
|
.flit_out_all (flit_out_all),
|
.assigned_ovc_num_all (assigned_ovc_num_all),
|
|
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
|
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.sel (sel),
|
.sel (sel),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
|
.credit_out_all(credit_out_all),
|
// .lk_destination_encoded_all (lk_destination_encoded_all),
|
// .lk_destination_encoded_all (lk_destination_encoded_all),
|
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
|
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
|
.destport_clear_all (destport_clear_all),
|
.destport_clear (destport_clear),
|
.vc_weight_is_consumed_all (vc_weight_is_consumed_all),
|
.vc_weight_is_consumed_all (vc_weight_is_consumed_all),
|
.iport_weight_is_consumed_all (iport_weight_is_consumed_all),
|
.iport_weight_is_consumed_all (iport_weight_is_consumed_all),
|
.iport_weight_all(iport_weight_all),
|
.iport_weight_all(iport_weight_all),
|
.oports_weight_all(oports_weight_all),
|
.oports_weight_all(oports_weight_all),
|
.granted_dest_port_all(granted_dest_port_all),
|
.granted_dest_port_all(granted_dest_port_all),
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| Line 235... |
Line 225... |
output_ports #(
|
output_ports #(
|
.P (P)
|
.P (P)
|
)
|
)
|
output_ports
|
output_ports
|
(
|
(
|
|
|
.vsa_ovc_allocated_all (vsa_ovc_allocated_all),
|
.vsa_ovc_allocated_all (vsa_ovc_allocated_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.assigned_ovc_num_all (assigned_ovc_num_all),
|
|
.ovc_is_assigned_all (ovc_is_assigned_all),
|
|
.dest_port_all (dest_port_all),
|
.dest_port_all (dest_port_all),
|
.nonspec_granted_dest_port_all (nonspec_granted_dest_port_all),
|
.nonspec_granted_dest_port_all (nonspec_granted_dest_port_all),
|
.credit_in_all (credit_in_all),
|
.credit_in_all (credit_in_all),
|
.nonspec_first_arbiter_granted_ivc_all (nonspec_first_arbiter_granted_ivc_all),
|
.nonspec_first_arbiter_granted_ivc_all (nonspec_first_arbiter_granted_ivc_all),
|
.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
|
.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
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| Line 258... |
Line 247... |
.crossbar_flit_out_wr_all (crossbar_flit_out_wr_all),
|
.crossbar_flit_out_wr_all (crossbar_flit_out_wr_all),
|
.any_ovc_granted_in_outport_all ( any_ovc_granted_in_outport_all),
|
.any_ovc_granted_in_outport_all ( any_ovc_granted_in_outport_all),
|
.vsa_ovc_released_all (vsa_ovc_released_all),
|
.vsa_ovc_released_all (vsa_ovc_released_all),
|
.vsa_credit_decreased_all(vsa_credit_decreased_all),
|
.vsa_credit_decreased_all(vsa_credit_decreased_all),
|
.oport_info (oport_info),
|
.oport_info (oport_info),
|
|
.ivc_info(ivc_info),
|
.ovc_info (ovc_info),
|
.ovc_info (ovc_info),
|
.smart_ctrl_in(smart_ctrl_in),
|
.smart_ctrl_in(smart_ctrl_in),
|
.vsa_ctrl_in(vsa_ctrl_in),
|
.vsa_ctrl_in(vsa_ctrl_in),
|
.ssa_ctrl_in(ssa_ctrl),
|
.ssa_ctrl_in(ssa_ctrl),
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.credit_init_val_in(credit_init_val_in)
|
.credit_init_val_in(credit_init_val_in)
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| Line 271... |
Line 261... |
vc_alloc_request_gen #(
|
vc_alloc_request_gen #(
|
.P(P)
|
.P(P)
|
)
|
)
|
vc_alloc_req_gen
|
vc_alloc_req_gen
|
(
|
(
|
|
.ivc_info(ivc_info),
|
.ovc_avalable_all(ovc_avalable_all),
|
.ovc_avalable_all(ovc_avalable_all),
|
.dest_port_encoded_all(dest_port_encoded_all),
|
|
.ivc_request_all(ivc_request_all),
|
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
|
.dest_port_decoded_all(dest_port_all),
|
.dest_port_decoded_all(dest_port_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.candidate_ovc_all(candidate_ovc_all),
|
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.sel(sel),
|
.sel(sel),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.destport_clear_all(destport_clear_all),
|
.destport_clear(destport_clear),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
//.ssa_ivc_num_getting_ovc_grant_all(nla_ivc_num_getting_ovc_grant_all),
|
//.ssa_ivc_num_getting_ovc_grant_all(nla_ivc_num_getting_ovc_grant_all),
|
.smart_ctrl_in (smart_ctrl_in),
|
.smart_ctrl_in (smart_ctrl_in),
|
.ssa_ctrl_in (ssa_ctrl)
|
.ssa_ctrl_in (ssa_ctrl)
|
);
|
);
|
| Line 309... |
Line 297... |
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
|
|
|
|
assign pck_is_single_flit_all =
|
|
/* verilator lint_off WIDTH */
|
|
(PCK_TYPE == "SINGLE_FLIT")? {PV{1'b1}} :
|
|
/* verilator lint_on WIDTH */
|
|
(MIN_PCK_SIZE == 1)? flit_is_tail_all & ~ovc_is_assigned_all : {PV{1'b0}};
|
|
|
|
register #(.W(PV)) credit_reg (.in(ivc_num_getting_sw_grant),.reset(reset),.clk(clk),.out(credit_out_all));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| Line 333... |
Line 313... |
ss_allocator #(
|
ss_allocator #(
|
.P(P)
|
.P(P)
|
)
|
)
|
the_ssa
|
the_ssa
|
(
|
(
|
|
.ivc_info(ivc_info),
|
.flit_in_wr_all(flit_in_wr_all),
|
.flit_in_wr_all(flit_in_wr_all),
|
.flit_in_all(flit_in_all),
|
.flit_in_all(flit_in_all),
|
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
|
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
|
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
|
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
|
.ovc_avalable_all(ovc_avalable_all),
|
.ovc_avalable_all(ovc_avalable_all),
|
.ivc_request_all(ivc_request_all),
|
|
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
|
|
.dest_port_encoded_all(dest_port_encoded_all),
|
|
.assigned_ovc_num_all(assigned_ovc_num_all),
|
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.ssa_ctrl_o(ssa_ctrl)
|
.ssa_ctrl_o(ssa_ctrl)
|
);
|
);
|
|
|
| Line 415... |
Line 391... |
input [V-1 :0] wr_in;
|
input [V-1 :0] wr_in;
|
input [V-1 :0] credit_in;
|
input [V-1 :0] credit_in;
|
output [V-1 :0] nearly_full_vc;
|
output [V-1 :0] nearly_full_vc;
|
output [V-1 : 0] full_vc;
|
output [V-1 : 0] full_vc;
|
output [V-1 :0] empty_vc;
|
output [V-1 :0] empty_vc;
|
output reg [V-1 :0] cand_vc;
|
output [V-1 :0] cand_vc;
|
input cand_wr_vc_en;
|
input cand_wr_vc_en;
|
input clk;
|
input clk;
|
input reset;
|
input reset;
|
|
|
|
|
| Line 434... |
Line 410... |
|
|
|
|
localparam DEPTH_WIDTH = log2(B+1);
|
localparam DEPTH_WIDTH = log2(B+1);
|
|
|
|
|
reg [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];
|
logic [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];
|
|
logic [DEPTH_WIDTH-1 : 0] credit_next [V-1 : 0];
|
wire [V-1 : 0] cand_vc_next;
|
wire [V-1 : 0] cand_vc_next;
|
|
|
wire [V-1 :0] request;
|
wire [V-1 :0] request;
|
|
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for(i=0;i
|
for(i=0;i
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
pronoc_register_reset_init #(
|
if(reset)begin
|
.W(DEPTH_WIDTH)
|
credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
|
)reg1(
|
end else begin
|
.in(credit_next[i]),
|
if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
|
.reset(reset),
|
if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
|
.clk(clk),
|
end //reset
|
.out(credit[i]),
|
|
.reset_to(credit_init_val_in[i][DEPTH_WIDTH-1:0])
|
|
);
|
|
|
|
|
|
|
|
always @ ( * )begin
|
|
credit_next[i] = credit [i];
|
|
if( wr_in[i] && ~credit_in[i]) credit_next[i] = credit[i]-1'b1;
|
|
if( ~wr_in[i] && credit_in[i]) credit_next[i] = credit[i]+1'b1;
|
end//always
|
end//always
|
|
|
assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});
|
assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});
|
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
|
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
|
assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
|
assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
|
| Line 477... |
Line 463... |
.request (request),
|
.request (request),
|
.grant (cand_vc_next),
|
.grant (cand_vc_next),
|
.any_grant ()
|
.any_grant ()
|
);
|
);
|
|
|
|
logic [V-1 : 0] cand_vc_ld_next;
|
|
pronoc_register #(.W(V)) reg2 (.in(cand_vc_ld_next ), .out(cand_vc), .reset(reset), .clk(clk));
|
|
|
|
always @ ( *) begin
|
`ifdef SYNC_RESET_MODE
|
cand_vc_ld_next = cand_vc;
|
always @ (posedge clk )begin
|
if(cand_wr_vc_en) cand_vc_ld_next = cand_vc_next;
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if (reset) cand_vc <= {V{1'b0}};
|
|
else if(cand_wr_vc_en) cand_vc <= cand_vc_next;
|
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
/*************************
|
/*************************
|
vc_alloc_request_gen
|
vc_alloc_request_gen
|
| Line 509... |
Line 487... |
#(
|
#(
|
|
|
parameter P = 5
|
parameter P = 5
|
|
|
)(
|
)(
|
|
ivc_info,
|
ovc_avalable_all,
|
ovc_avalable_all,
|
dest_port_encoded_all,
|
|
candidate_ovc_all,
|
|
ivc_request_all,
|
|
ovc_is_assigned_all,
|
|
dest_port_decoded_all,
|
dest_port_decoded_all,
|
masked_ovc_request_all,
|
masked_ovc_request_all,
|
port_pre_sel,
|
port_pre_sel,
|
swap_port_presel,
|
swap_port_presel,
|
sel,
|
sel,
|
reset,
|
reset,
|
clk,
|
clk,
|
destport_clear_all,
|
destport_clear,
|
ivc_num_getting_ovc_grant,
|
ivc_num_getting_ovc_grant,
|
smart_ctrl_in,
|
smart_ctrl_in,
|
ssa_ctrl_in
|
ssa_ctrl_in
|
);
|
);
|
|
|
| Line 534... |
Line 509... |
PVV = PV * V,
|
PVV = PV * V,
|
PVP_1 = PV * P_1,
|
PVP_1 = PV * P_1,
|
PVDSTPw= PV * DSTPw;
|
PVDSTPw= PV * DSTPw;
|
|
|
|
|
|
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PVDSTPw-1 : 0] dest_port_encoded_all;
|
|
input [PV-1 : 0] ivc_request_all;
|
|
input [PV-1 : 0] ovc_is_assigned_all;
|
|
input [PVP_1-1 : 0] dest_port_decoded_all;
|
input [PVP_1-1 : 0] dest_port_decoded_all;
|
output [PVV-1 : 0] masked_ovc_request_all;
|
output [PVV-1 : 0] masked_ovc_request_all;
|
input [PVV-1 : 0] candidate_ovc_all;
|
|
input [PPSw-1 : 0] port_pre_sel;
|
input [PPSw-1 : 0] port_pre_sel;
|
output [PV-1 : 0] sel;
|
output [PV-1 : 0] sel;
|
output [PV-1 : 0] swap_port_presel;
|
output [PV-1 : 0] swap_port_presel;
|
input reset;
|
input reset;
|
input clk;
|
input clk;
|
output [PVDSTPw-1 : 0] destport_clear_all;
|
output [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
|
|
|
input [PV-1 : 0] ivc_num_getting_ovc_grant;
|
input [PV-1 : 0] ivc_num_getting_ovc_grant;
|
input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
|
input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
|
input smart_ctrl_t smart_ctrl_in [P-1: 0];
|
input smart_ctrl_t smart_ctrl_in [P-1: 0];
|
|
input ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
|
|
|
|
wire [PV-1 : 0] ivc_request_all;
|
|
wire [PVDSTPw-1 : 0] dest_port_encoded_all;
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|
wire [PVV-1 : 0] candidate_ovc_all;
|
|
wire [PV-1 : 0] ovc_is_assigned_all;
|
|
|
wire [PV-1 : 0] ovc_avalable_all_masked;
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wire [PV-1 : 0] ovc_avalable_all_masked;
|
wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
|
wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
|
|
wire [PVDSTPw-1 : 0] destport_clear_all;
|
|
|
genvar i;
|
genvar i,j;
|
generate
|
generate
|
|
|
for(i=0;i< P;i=i+1) begin :p_
|
for(i=0;i< P;i=i+1) begin :p_
|
assign ovc_avalable_all_masked [(i+1)*V-1 : i*V] = (SMART_EN)? ovc_avalable_all [(i+1)*V-1 : i*V] & ~smart_ctrl_in[i].mask_available_ovc : ovc_avalable_all [(i+1)*V-1 : i*V];
|
assign ovc_avalable_all_masked [(i+1)*V-1 : i*V] = (SMART_EN)? ovc_avalable_all [(i+1)*V-1 : i*V] & ~smart_ctrl_in[i].mask_available_ovc : ovc_avalable_all [(i+1)*V-1 : i*V];
|
assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
|
assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
|
|
for(j=0;j< V;j=j+1) begin :V_
|
|
assign ivc_request_all[i*V+j] = ivc_info[i][j].ivc_req;
|
|
assign ovc_is_assigned_all[i*V+j] = ivc_info[i][j].ovc_is_assigned;
|
|
assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1 : (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
|
|
assign candidate_ovc_all[(i*V+j+1)*V-1 : (i*V+j)*V]= ivc_info[i][j].candidate_ovc;
|
|
assign destport_clear [i][j]=destport_clear_all [(i*V+j+1)*DSTPw-1 : (i*V+j)*DSTPw];
|
|
end
|
end//for
|
end//for
|
|
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
| Line 572... |
Line 559... |
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
vc_alloc_request_gen_determinstic #(
|
vc_alloc_request_gen_determinstic #(
|
.P(P),
|
.P(P),
|
.V(V),
|
.V(V),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN),
|
|
.CAST_TYPE(CAST_TYPE)
|
)
|
)
|
vc_request_gen
|
vc_request_gen
|
(
|
(
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.ivc_request_all(ivc_request_all),
|
.ivc_request_all(ivc_request_all),
|
| Line 675... |
Line 663... |
|
|
|
|
module vc_alloc_request_gen_determinstic #(
|
module vc_alloc_request_gen_determinstic #(
|
parameter P = 5,
|
parameter P = 5,
|
parameter V = 4,
|
parameter V = 4,
|
parameter SELF_LOOP_EN="NO"
|
parameter SELF_LOOP_EN="NO",
|
|
parameter CAST_TYPE = "UNICAST"
|
|
|
)(
|
)(
|
ovc_avalable_all,
|
ovc_avalable_all,
|
candidate_ovc_all,
|
candidate_ovc_all,
|
ivc_request_all,
|
ivc_request_all,
|
| Line 712... |
Line 701... |
|
|
|
|
genvar i;
|
genvar i;
|
|
|
generate
|
generate
|
if(SELF_LOOP_EN == "NO") begin
|
if(SELF_LOOP_EN == "NO" ) begin :nslp
|
//remove available ovc of receiver port
|
//remove available ovc of receiver port
|
for(i=0;i< P;i=i+1) begin :port_loop
|
for(i=0;i< P;i=i+1) begin :port_loop
|
if(i==0) begin : first assign ovc_avalable_perport[i]=ovc_avalable_all [PV-1 : V]; end
|
if(i==0) begin : first assign ovc_avalable_perport[i]=ovc_avalable_all [PV-1 : V]; end
|
else if(i==(P-1)) begin : last assign ovc_avalable_perport[i]=ovc_avalable_all [PV-V-1 : 0]; end
|
else if(i==(P-1)) begin : last assign ovc_avalable_perport[i]=ovc_avalable_all [PV-V-1 : 0]; end
|
else begin : midle assign ovc_avalable_perport[i]={ovc_avalable_all [PV-1 : (i+1)*V],ovc_avalable_all [(i*V)-1 : 0]}; end
|
else begin : midle assign ovc_avalable_perport[i]={ovc_avalable_all [PV-1 : (i+1)*V],ovc_avalable_all [(i*V)-1 : 0]}; end
|
end
|
end
|
end else begin
|
end else begin :slp
|
for(i=0;i< P;i=i+1) begin :port_loop
|
for(i=0;i< P;i=i+1) begin :port_loop
|
assign ovc_avalable_perport[i]=ovc_avalable_all;
|
assign ovc_avalable_perport[i]=ovc_avalable_all;
|
end
|
end
|
end
|
end
|
// IVC loop
|
// IVC loop
|
