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`timescale 1ns/1ps
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`include "pronoc_def.v"
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//`define MONITORE_PATH
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//`define MONITORE_PATH
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/**********************************************************************
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/**********************************************************************
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** File: input_ports.v
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** File: input_ports.v
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**
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**
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input [VV-1 : 0] assigned_ovc_num;
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input [VV-1 : 0] assigned_ovc_num;
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input [V-1 : 0] sel;
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input [V-1 : 0] sel;
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input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
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input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
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input [V-1 : 0] ssa_ivc_num_getting_sw_grant;
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input [V-1 : 0] ssa_ivc_num_getting_sw_grant;
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input [(DSTPw*V)-1 : 0] destport_clear;
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input [(DSTPw*V)-1 : 0] destport_clear;
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output reg [WEIGHTw-1 : 0] iport_weight;
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output [WEIGHTw-1 : 0] iport_weight;
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output [V-1 : 0] vc_weight_is_consumed;
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output [V-1 : 0] vc_weight_is_consumed;
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output iport_weight_is_consumed;
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output iport_weight_is_consumed;
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input refresh_w_counter;
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input refresh_w_counter;
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input [P_1-1 : 0] granted_dest_port;
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input [P_1-1 : 0] granted_dest_port;
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output [WP-1 : 0] oports_weight;
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output [WP-1 : 0] oports_weight;
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wire [VDSTPw-1 : 0] lk_destination_encoded;
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wire [VDSTPw-1 : 0] lk_destination_encoded;
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wire [EAw-1 : 0] dest_e_addr_in;
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wire [EAw-1 : 0] dest_e_addr_in;
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wire [EAw-1 : 0] src_e_addr_in;
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wire [EAw-1 : 0] src_e_addr_in;
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wire [V-1 : 0] vc_num_in;
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wire [V-1 : 0] vc_num_in;
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wire [V-1 : 0] hdr_flit_wr,flit_wr;
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wire [V-1 : 0] hdr_flit_wr,flit_wr;
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reg [V-1 : 0] hdr_flit_wr_delayed;
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wire [V-1 : 0] hdr_flit_wr_delayed;
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wire [V-1 : 0] class_rd_fifo,dst_rd_fifo;
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wire [V-1 : 0] class_rd_fifo,dst_rd_fifo;
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reg [V-1 : 0] lk_dst_rd_fifo;
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wire [V-1 : 0] lk_dst_rd_fifo;
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wire [DSTPw-1 : 0] lk_destination_in_encoded;
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wire [DSTPw-1 : 0] lk_destination_in_encoded;
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wire [WEIGHTw-1 : 0] weight_in;
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wire [WEIGHTw-1 : 0] weight_in;
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wire [Fw-1 : 0] buffer_out;
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wire [Fw-1 : 0] buffer_out;
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wire hdr_flg_in,tail_flg_in;
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wire hdr_flg_in,tail_flg_in;
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wire [V-1 : 0] ivc_not_empty;
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wire [V-1 : 0] ivc_not_empty;
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wire [Cw-1 : 0] class_out [V-1 : 0];
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wire [Cw-1 : 0] class_out [V-1 : 0];
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wire [VELw-1 : 0] endp_localp_num;
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wire [VELw-1 : 0] endp_localp_num;
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wire [ELw-1 : 0] endp_l_in;
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wire [ELw-1 : 0] endp_l_in;
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logic [WEIGHTw-1 : 0] iport_weight_next;
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//extract header flit info
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//extract header flit info
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extract_header_flit_info #(
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extract_header_flit_info #(
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.DATA_w(0)
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.DATA_w(0)
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)
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)
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`endif
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`endif
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// synthesis translate_on
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// synthesis translate_on
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// synopsys translate_on
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// synopsys translate_on
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`ifdef SYNC_RESET_MODE
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pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
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always @ (posedge clk )begin
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.in (iport_weight_next ),
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`else
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.reset (reset ),
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always @ (posedge clk or posedge reset)begin
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.clk (clk ),
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`endif
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.out (iport_weight ));
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if(reset) begin
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iport_weight <= 1;
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end else begin
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always @ (*)begin
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if(hdr_flit_wr != {V{1'b0}}) iport_weight <= (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
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iport_weight_next = iport_weight;
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end
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if(hdr_flit_wr != {V{1'b0}}) iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
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end
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end
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// genrate write enable for lk_routing result with one clock cycle latency after reciveing the flit
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// genrate write enable for lk_routing result with one clock cycle latency after reciveing the flit
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`ifdef SYNC_RESET_MODE
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always @ (posedge clk )begin
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pronoc_register #(.W(V)) reg1(
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`else
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.in (hdr_flit_wr ),
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always @ (posedge clk or posedge reset)begin
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.reset (reset ),
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`endif
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.clk (clk ),
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if(reset) begin
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.out (hdr_flit_wr_delayed ));
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hdr_flit_wr_delayed <= {V{1'b0}};
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//lk_dst_rd_fifo <= {V{1'b0}};
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end else begin
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hdr_flit_wr_delayed <= hdr_flit_wr;
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// lk_dst_rd_fifo <= dst_rd_fifo;
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end
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end
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genvar i;
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genvar i;
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generate
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generate
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
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if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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flit_buffer #(
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flit_buffer #(
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.V(V),
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.B(B), // buffer space :flit per VC
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.B(B), // buffer space :flit per VC
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.PCK_TYPE(PCK_TYPE),
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.Fw(Fw),
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.DEBUG_EN(DEBUG_EN),
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.SSA_EN(SSA_EN)
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.SSA_EN(SSA_EN)
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)
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)
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the_flit_buffer
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the_flit_buffer
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(
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(
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.din(flit_in), // Data in
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.din(flit_in), // Data in
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.rd_en(any_ivc_sw_request_granted), // Read the next word
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.rd_en(any_ivc_sw_request_granted), // Read the next word
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.dout(buffer_out), // Data out
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.dout(buffer_out), // Data out
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.vc_not_empty(ivc_not_empty),
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.vc_not_empty(ivc_not_empty),
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.ssa_rd(ssa_ivc_num_getting_sw_grant)
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.ssa_rd(ssa_ivc_num_getting_sw_grant),
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.multiple_dest(),
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.sub_rd_ptr_ld(),
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.flit_is_tail()
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);
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);
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localparam VCw = V *Cw;
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localparam VCw = V *Cw;
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end else begin :spec//not nonspec comb
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end else begin :spec//not nonspec comb
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flit_buffer #(
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flit_buffer #(
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.V(V),
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.B(B), // buffer space :flit per VC
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.B(B), // buffer space :flit per VC
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.PCK_TYPE(PCK_TYPE),
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.Fw(Fw),
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.DEBUG_EN(DEBUG_EN),
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.SSA_EN(SSA_EN)
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.SSA_EN(SSA_EN)
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)
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)
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the_flit_buffer
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the_flit_buffer
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(
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(
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.din(flit_in), // Data in
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.din(flit_in), // Data in
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.rd_en(any_ivc_sw_request_granted), // Read the next word
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.rd_en(any_ivc_sw_request_granted), // Read the next word
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.dout(buffer_out), // Data out
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.dout(buffer_out), // Data out
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.vc_not_empty(ivc_not_empty),
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.vc_not_empty(ivc_not_empty),
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.ssa_rd(ssa_ivc_num_getting_sw_grant)
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.ssa_rd(ssa_ivc_num_getting_sw_grant),
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.multiple_dest(),
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.sub_rd_ptr_ld(),
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.flit_is_tail()
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);
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);
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end
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end
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endgenerate
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endgenerate
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.clk (clk)
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.clk (clk)
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);
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);
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assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
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assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
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`ifdef SYNC_RESET_MODE
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always @ (posedge clk )begin
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pronoc_register #(.W(V)) reg2(
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`else
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.in (dst_rd_fifo ),
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always @ (posedge clk or posedge reset)begin
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.reset (reset ),
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`endif
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.clk (clk ),
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if(reset) begin
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.out (lk_dst_rd_fifo ));
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lk_dst_rd_fifo <= {V{1'b0}};
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end else begin
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lk_dst_rd_fifo <= dst_rd_fifo;
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end
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end//always
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assign dst_rd_fifo = reset_ivc;
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assign dst_rd_fifo = reset_ivc;
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assign class_rd_fifo = (C>1)? reset_ivc : {V{1'bx}};
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assign class_rd_fifo = (C>1)? reset_ivc : {V{1'bx}};
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assign ivc_request = ivc_not_empty;
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assign ivc_request = ivc_not_empty;
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