URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [mesh_torus_routting.v] - Diff between revs 48 and 54

Rev 48	Rev 54
Line 48...	Line 48...
`input [Yw-1 : 0] dest_y;`	`input [Yw-1 : 0] dest_y;`
`input [P_1-1 : 0] destport_encoded;`	`input [P_1-1 : 0] destport_encoded;`
`output [P_1-1 : 0] lkdestport_encoded;`	`output [P_1-1 : 0] lkdestport_encoded;`
`input reset,clk;`	`input reset,clk;`

`reg [Xw-1 : 0] destx_delayed;`	`wire [Xw-1 : 0] destx_delayed;`
`reg [Yw-1 : 0] desty_delayed;`	`wire [Yw-1 : 0] desty_delayed;`
`reg [P_1-1 : 0] destport_delayed;`	`wire [P_1-1 : 0] destport_delayed;`


`// routing algorithm`	`// routing algorithm`
`generate`	`generate`
`/* verilator lint_off WIDTH */`	`/* verilator lint_off WIDTH */`
Line 98...	Line 98...


`end`	`end`
`endgenerate`	`endgenerate`

	`pronoc_register #(.W(Xw) ) reg1 (.in(dest_x ), .out(destx_delayed), .reset(reset), .clk(clk));`
`ifdef SYNC_RESET_MODE	`pronoc_register #(.W(Yw) ) reg2 (.in(dest_y ), .out(desty_delayed), .reset(reset), .clk(clk));`
`always @ (posedge clk )begin`	`pronoc_register #(.W(P_1)) reg3 (.in(destport_encoded ), .out(destport_delayed), .reset(reset), .clk(clk));`
`else
`always @ (posedge clk or posedge reset)begin`
`endif
`if(reset)begin`
`destx_delayed <= {Xw{1'b0}};`
`desty_delayed <= {Yw{1'b0}};`
`destport_delayed <= {P_1{1'b0}};`
`end else begin`
`destx_delayed <= dest_x;`
`desty_delayed <= dest_y;`
`destport_delayed <= destport_encoded;`
`end//else reset`
`end//always`

`endmodule`	`endmodule`