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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [noc_filelist.f] - Diff between revs 48 and 54

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Rev 48	Rev 54
Line 1...	Line 1...
`+incdir+./`	`+incdir+./`
	`+incdir+./../`
`./pronoc_pkg.sv`	`./pronoc_pkg.sv`
`./../main_comp.v`	`./../main_comp.v`
`./../arbiter.v`	`./../arbiter.v`
`./class_table.v`	`./class_table.v`
`./ss_allocator.sv`	`./ss_allocator.sv`
`./route_torus.v`	`./route_torus.v`
`./header_flit.sv`	`./header_flit.sv`
`./noc_top.sv`	`./noc_top.sv`
`./fattree_noc_top.sv`	`./fattree_noc_top.sv`
`./fattree_route.v`	`./fattree_route.v`
`./comb_nonspec.v`	`./comb_nonspec.sv`
`./inout_ports.sv`	`./inout_ports.sv`
`./wrra.v`	`./wrra.v`
`./input_ports.sv`	`./input_ports.sv`
`./tree_noc_top.sv`	`./tree_noc_top.sv`
`./tree_route.v`	`./tree_route.v`
`./comb-spec1.v`	`./comb-spec1.v`
`./combined_vc_sw_alloc.v`	`./combined_vc_sw_alloc.sv`
`./mesh_torus_routting.v`	`./mesh_torus_routting.v`
`./baseline.v`	`./baseline.v`
`./comb_spec2.v`	`./comb_spec2.v`
`./flit_buffer_reg_bas.v`	`./flit_buffer_reg_bas.v`
`./route_mesh.v`	`./route_mesh.v`
Line 28...	Line 29...
`./output_ports.sv`	`./output_ports.sv`
`./routing.v`	`./routing.v`
`./router_two_stage.sv`	`./router_two_stage.sv`
`./crossbar.v`	`./crossbar.v`
`./iport_reg_base.sv`	`./iport_reg_base.sv`
`./flit_buffer.v`	`./flit_buffer.sv`
`./mesh_torus.v`	`./mesh_torus.sv`
`./debug.v`	`./debug.v`
`./router_top.sv`	`./router_top.sv`
`./mesh_torus_noc_top.sv`	`./mesh_torus_noc_top.sv`
`./star_noc.sv`	`./star_noc.sv`
`./fmesh.sv`	`./fmesh.sv`
`./packet_injector.sv`	`./packet_injector.sv`
	`./multicast.sv`




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