OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [noc_top.sv] - Diff between revs 48 and 54

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 48 Rev 54
Line 1... Line 1...
// synthesis translate_off
`include "pronoc_def.v"
`timescale 1ns / 1ps
 
// synthesis translate_on
 
 
 
 
 
/**********************************************************************
/**********************************************************************
**    File:  noc_top.sv
**    File:  noc_top.sv
**
**
**    Copyright (C) 2014-2017  Alireza Monemi
**    Copyright (C) 2014-2017  Alireza Monemi
**
**
Line 35... Line 31...
        import pronoc_pkg::*;
        import pronoc_pkg::*;
(
(
        reset,
        reset,
        clk,
        clk,
        chan_in_all,
        chan_in_all,
        chan_out_all
        chan_out_all,
 
        router_event
);
);
 
 
 
 
        input   clk,reset;
        input   clk,reset;
        //local ports
        //Endpoints ports
        input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
        input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
        output  smartflit_chanel_t chan_out_all [NE-1 : 0];
        output  smartflit_chanel_t chan_out_all [NE-1 : 0];
 
        //Events
 
        output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
 
 
 
 
 
 
 
 
        generate
        generate
Line 56... Line 54...
        /* verilator lint_on WIDTH */
        /* verilator lint_on WIDTH */
                mesh_torus_noc_top noc_top (
                mesh_torus_noc_top noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all )
                        .chan_out_all  (chan_out_all ),
 
                        .router_event  (router_event )
                );
                );
 
 
 
 
    end else if (TOPOLOGY == "FATTREE") begin : fat_
    end else if (TOPOLOGY == "FATTREE") begin : fat_
 
 
        fattree_noc_top noc_top (
        fattree_noc_top noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all )
                        .chan_out_all  (chan_out_all ),
 
                        .router_event  (router_event )
        );
        );
 
 
 
 
    end else if (TOPOLOGY == "TREE") begin : tree_
    end else if (TOPOLOGY == "TREE") begin : tree_
        tree_noc_top  noc_top (
        tree_noc_top  noc_top (
                .reset         (reset        ),
                .reset         (reset        ),
                .clk           (clk          ),
                .clk           (clk          ),
                .chan_in_all   (chan_in_all  ),
                .chan_in_all   (chan_in_all  ),
                .chan_out_all  (chan_out_all )
                .chan_out_all  (chan_out_all ),
 
                .router_event  (router_event )
        );
        );
    end else if (TOPOLOGY == "STAR") begin : star_
    end else if (TOPOLOGY == "STAR") begin : star_
        star_noc_top  noc_top (
        star_noc_top  noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all )
                        .chan_out_all  (chan_out_all ),
 
                        .router_event  (router_event )
                );
                );
 
 
    end else begin :custom_
    end else begin :custom_
 
 
        custom_noc_top noc_top (
        custom_noc_top noc_top (
                        .reset         (reset        ),
                        .reset         (reset        ),
                        .clk           (clk          ),
                        .clk           (clk          ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_in_all   (chan_in_all  ),
                        .chan_out_all  (chan_out_all )
                        .chan_out_all  (chan_out_all ),
 
                        .router_event  (router_event )
                );
                );
 
 
    end
    end
    endgenerate
    endgenerate
endmodule
endmodule
Line 104... Line 107...
 
 
 
 
 
 
 
 
/**********************************
/**********************************
The noc top module that can be caled in Verilog module.
The noc top module that can be called in Verilog module.
 
 
***********************************/
***********************************/
 
 
module  noc_top_v
module  noc_top_v
   import pronoc_pkg::*;
   import pronoc_pkg::*;
Line 139... Line 142...
 
 
        noc_top the_top(
        noc_top the_top(
                .reset(reset),
                .reset(reset),
                .clk(clk),
                .clk(clk),
                .chan_in_all(chan_in_all),
                .chan_in_all(chan_in_all),
                .chan_out_all(chan_out_all)
                .chan_out_all(chan_out_all),
 
                .router_event  (  )
        );
        );
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.