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`timescale 1ns / 1ps
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`include "pronoc_def.v"
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/**************************************
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/**************************************
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* Module: router_bypass
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* Module: router_bypass
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* Date:2020-11-24
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* Date:2020-11-24
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* Author: alireza
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* Author: alireza
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*
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*
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* Description:
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* Description:
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* This file contains HDL modules that can be added
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* This file contains HDL modules that can be added
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* to a 3-stage NoC router and provide router bypassing
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* to a 2-stage NoC router and provides router bypassing
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***************************************/
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***************************************/
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/**************************
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/**************************
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* SMART_flags_gen:
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* SMART_flags_gen:
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* generate SMART flags based on NoC parameter, current router's port and address,
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* generate SMART flags based on NoC parameter, current router's port and address,
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* smart_flag_o indicates how many more router in direct line can be bypassed
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* smart_flag_o indicates how many more router in direct line can be bypassed
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* if SPB_OPORT_NUM is also one of the possible output port in
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* if SPB_OPORT_NUM is also one of the possible output port in
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* lk-ahead routing, The packet can by-pass the next router once the bypassing condition are met
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* lk-ahead routing, The packet can by-pass the next router once the bypassing condition are met
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***************************/
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***************************/
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module register #(parameter W=1)(
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`include "pronoc_def.v"
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input [W-1:0] in,
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input reset,
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input clk,
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output reg [W-1:0] out
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);
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`ifdef SYNC_RESET_MODE
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always @ (posedge clk )begin
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`else
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always @ (posedge clk or posedge reset)begin
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`endif
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if(reset) begin
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out<={W{1'b0}};
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end else begin
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out<=in;
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end
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end
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endmodule
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module reduction_or #(
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module reduction_or #(
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parameter W = 5,//out width
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parameter W = 5,//out width
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parameter N = 4 //array lenght
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parameter N = 4 //array lenght
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Line 95... |
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endmodule
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endmodule
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module onehot_mux_1D_reverse #(
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parameter W = 5,//out width p
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parameter N = 4 //sel width v
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)(
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input [W*N-1 : 0] in,
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input [N-1 : 0] sel,
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output [W-1 : 0] out
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);
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wire [N-1 : 0] in_array [W-1 : 0];
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wire [W-1 : 0] in_array2[N-1 : 0];
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genvar i,j;
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generate
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for (i=0;i
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assign in_array[i] = in[(i+1)*N-1 : i*N];
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for (j=0;j
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assign in_array2[j][i] = in_array[i][j];
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end
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end
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endgenerate
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onehot_mux_2D #(
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.W (N ),
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.N (W )
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) onehot_mux_2D (
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.in (in_array2 ),
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.sel (sel ),
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.out (out ));
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endmodule
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module header_flit_info
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module header_flit_info
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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#(
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#(
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Line 312... |
assign mask_gen[z][j][i] = non_assigned_vc_req[i][j] & ivc_info[i][j].destport_one_hot[z];
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assign mask_gen[z][j][i] = non_assigned_vc_req[i][j] & ivc_info[i][j].destport_one_hot[z];
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end
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end
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assign ovc_locally_requested_next[i][j]=|mask_gen[i][j];
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assign ovc_locally_requested_next[i][j]=|mask_gen[i][j];
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end//V
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end//V
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register #(.W(V)) reg1 (.in(ovc_locally_requested_next[i] ), .reset(reset), .clk(clk), .out(ovc_locally_requested[i]));
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pronoc_register #(.W(V)) reg1 (.in(ovc_locally_requested_next[i] ), .reset(reset), .clk(clk), .out(ovc_locally_requested[i]));
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onehot_mux_2D #(.W(SMART_IVC_w),.N(V)) mux1 ( .in(smart_ivc_info[i]), .sel(iport_info[i].swa_first_level_grant), .out(smart_ivc_mux[i]));
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onehot_mux_2D #(.W(SMART_IVC_w),.N(V)) mux1 ( .in(smart_ivc_info[i]), .sel(iport_info[i].swa_first_level_grant), .out(smart_ivc_mux[i]));
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assign smart_chanel_next[i].dest_e_addr= smart_vc_info_o[i].dest_e_addr;
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assign smart_chanel_next[i].dest_e_addr= smart_vc_info_o[i].dest_e_addr;
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assign smart_chanel_next[i].ovc= (smart_vc_info_o[i].ovc_is_assigned)? assigned_ovc[i] : oport_info[i].non_smart_ovc_is_allocated;
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assign smart_chanel_next[i].ovc= (smart_vc_info_o[i].ovc_is_assigned)? assigned_ovc[i] : oport_info[i].non_smart_ovc_is_allocated;
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assign smart_chanel_next[i].hdr_flit=~smart_vc_info_o[i].ovc_is_assigned;
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assign smart_chanel_next[i].hdr_flit=~smart_vc_info_o[i].ovc_is_assigned;
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assign smart_chanel_next[i].requests = (oport_info[i].any_ovc_granted)? {SMART_NUM{1'b1}}:{SMART_NUM{1'b0}} ;
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assign smart_chanel_next[i].requests = (oport_info[i].any_ovc_granted)? {SMART_NUM{1'b1}}:{SMART_NUM{1'b0}} ;
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assign smart_chanel_next[i].bypassed_num = {BYPASSw{1'b0}} ;
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if( ADD_PIPREG_AFTER_CROSSBAR == 1 ) begin :link_reg
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if( ADD_PIPREG_AFTER_CROSSBAR == 1 ) begin :link_reg
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register #(
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pronoc_register #(
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.W ( SMART_CHANEL_w )
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.W ( SMART_CHANEL_w )
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) register (
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) register (
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.in (smart_chanel_next[i] ),
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.in (smart_chanel_next[i] ),
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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Line 372... |
end else begin :no_link_reg
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end else begin :no_link_reg
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assign smart_chanel[i] = smart_chanel_next[i];
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assign smart_chanel[i] = smart_chanel_next[i];
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end
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end
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/*
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/*
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`ifdef SYNC_RESET_MODE
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always @ (`pronoc_clk_reset_edge )begin
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always @ (posedge clk )begin
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if(`pronoc_reset) begin
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`else
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always @ (posedge clk or posedge reset)begin
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`endif
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if(reset) begin
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smart_chanel[i].dest_e_addr<= {EAw{1'b0}};
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smart_chanel[i].dest_e_addr<= {EAw{1'b0}};
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smart_chanel[i].ovc<= {V{1'b0}};
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smart_chanel[i].ovc<= {V{1'b0}};
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smart_chanel[i].hdr_flit<=1'b0;
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smart_chanel[i].hdr_flit<=1'b0;
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end else begin
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end else begin
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smart_chanel[i].dest_e_addr<= smart_vc_info_o[i].dest_e_addr;
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smart_chanel[i].dest_e_addr<= smart_vc_info_o[i].dest_e_addr;
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Line 463... |
//smart_chanel_shifter
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//smart_chanel_shifter
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assign smart_forwardable[i] = | (ivc_forwardable[i] & smart_chanel_in[i].ovc);
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assign smart_forwardable[i] = | (ivc_forwardable[i] & smart_chanel_in[i].ovc);
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always @(*) begin
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always @(*) begin
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smart_chanel_shifted[i] = smart_chanel_in [i];
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smart_chanel_shifted[i] = smart_chanel_in [i];
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{smart_chanel_shifted[i].requests,rq[i]} =(smart_forwardable[i])? {1'b0,smart_chanel_in[i].requests}:{{SMART_NUM{1'b0}},smart_chanel_in[i].requests[0]};
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{smart_chanel_shifted[i].requests,rq[i]} =(smart_forwardable[i])? {1'b0,smart_chanel_in[i].requests}:{{SMART_NUM{1'b0}},smart_chanel_in[i].requests[0]};
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smart_chanel_shifted[i].bypassed_num = smart_chanel_in [i].bypassed_num +1'b1;
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end
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end
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assign smart_req[i]=rq[i];
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assign smart_req[i]=rq[i];
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// mux out smart chanel
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// mux out smart chanel
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assign smart_chanel_out[i] = (outport_is_granted[i])? smart_chanel_new[i] : smart_chanel_shifted[SS_PORT];
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assign smart_chanel_out[i] = (outport_is_granted[i])? smart_chanel_new[i] : smart_chanel_shifted[SS_PORT];
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Line 504... |
input [DSTPw-1 : 0] destport_coded_i;
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input [DSTPw-1 : 0] destport_coded_i;
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output goes_straight_o;
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output goes_straight_o;
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generate
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generate
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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if(TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" ) begin :twoD
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if(TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY =="FMESH" ) begin :twoD
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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if (SS_PORT_LOC == 0 || SS_PORT_LOC > 4) begin : local_ports
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if (SS_PORT_LOC == 0 || SS_PORT_LOC > 4) begin : local_ports
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assign goes_straight_o = 1'b0; // There is not a next router in this case at all
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assign goes_straight_o = 1'b0; // There is not a next router in this case at all
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end
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end
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else begin :non_local
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else begin :non_local
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Line 634... |
wire smart_req_valid_next = smart_requests_i & smart_ivc_i & goes_straight;
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wire smart_req_valid_next = smart_requests_i & smart_ivc_i & goes_straight;
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logic smart_req_valid;
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logic smart_req_valid;
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wire smart_hdr_flit_req_next = smart_req_valid_next & smart_hdr_flit;
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wire smart_hdr_flit_req_next = smart_req_valid_next & smart_hdr_flit;
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logic smart_hdr_flit_req;
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logic smart_hdr_flit_req;
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register #(.W(1)) req1 (.in(smart_req_valid_next), .reset(reset), .clk(clk), .out(smart_req_valid));
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pronoc_register #(.W(1)) req1 (.in(smart_req_valid_next), .reset(reset), .clk(clk), .out(smart_req_valid));
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register #(.W(1)) req2 (.in(smart_hdr_flit_req_next), .reset(reset), .clk(clk), .out(smart_hdr_flit_req));
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pronoc_register #(.W(1)) req2 (.in(smart_hdr_flit_req_next), .reset(reset), .clk(clk), .out(smart_hdr_flit_req));
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// condition1: new smart vc allocation condition
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// condition1: new smart vc allocation condition
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Line 687... |
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//mask the available SS OVC for local requests allocation if the following conditions met
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//mask the available SS OVC for local requests allocation if the following conditions met
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assign smart_mask_available_ss_ovc_o = smart_hdr_flit_req & ~ovc_locally_requested & condition2;
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assign smart_mask_available_ss_ovc_o = smart_hdr_flit_req & ~ovc_locally_requested & condition2;
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register #(.W(1)) credit(.in(smart_buff_space_decreased_o), .reset(reset), .clk(clk), .out(smart_credit_o));
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pronoc_register #(.W(1)) credit(.in(smart_buff_space_decreased_o), .reset(reset), .clk(clk), .out(smart_credit_o));
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endmodule
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endmodule
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Line 769... |
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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localparam LOCATED_IN_NI=
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localparam LOCATED_IN_NI=
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(TOPOLOGY=="RING" || TOPOLOGY=="LINE") ? (SW_LOC == 0 || SW_LOC>2) :
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(TOPOLOGY=="RING" || TOPOLOGY=="LINE") ? (SW_LOC == 0 || SW_LOC>2) :
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(TOPOLOGY =="MESH" || TOPOLOGY=="TORUS")? (SW_LOC == 0 || SW_LOC>4) : 0;
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(TOPOLOGY =="MESH" || TOPOLOGY=="TORUS" || TOPOLOGY == "FMESH")? (SW_LOC == 0 || SW_LOC>4) : 0;
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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// does the route computation for the current router
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// does the route computation for the current router
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conventional_routing #(
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conventional_routing #(
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.TOPOLOGY (TOPOLOGY ),
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.TOPOLOGY (TOPOLOGY ),
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| Line 775... |
Line 793... |
.src_e_addr ( ),// needed only for custom routing
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.src_e_addr ( ),// needed only for custom routing
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.dest_e_addr (smart_chanel_i.dest_e_addr ),
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.dest_e_addr (smart_chanel_i.dest_e_addr ),
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.destport (destport)
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.destport (destport)
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);
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);
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register #(.W(DSTPw)) reg1 (.in(destport), .reset(reset), .clk(clk), .out(smart_destport_o));
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pronoc_register #(.W(DSTPw)) reg1 (.in(destport), .reset(reset), .clk(clk), .out(smart_destport_o));
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check_straight_oport #(
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check_straight_oport #(
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.TOPOLOGY ( TOPOLOGY ),
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.TOPOLOGY ( TOPOLOGY ),
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.ROUTE_NAME ( ROUTE_NAME ),
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.ROUTE_NAME ( ROUTE_NAME ),
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.ROUTE_TYPE ( ROUTE_TYPE ),
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.ROUTE_TYPE ( ROUTE_TYPE ),
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| Line 809... |
Line 827... |
.src_e_addr ( ),// needed only for custom routing
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.src_e_addr ( ),// needed only for custom routing
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.dest_e_addr (smart_chanel_i.dest_e_addr ),
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.dest_e_addr (smart_chanel_i.dest_e_addr ),
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.destport (lkdestport)
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.destport (lkdestport)
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);
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);
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register #(.W(DSTPw)) reg2 (.in(lkdestport), .reset(reset), .clk(clk), .out(smart_lk_destport_o));
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pronoc_register #(.W(DSTPw)) reg2 (.in(lkdestport), .reset(reset), .clk(clk), .out(smart_lk_destport_o));
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wire [V-1 : 0] ss_ovc_crossbar_wr;//If asserted, a flit will be injected to ovc at next clk cycle
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wire [V-1 : 0] ss_ovc_crossbar_wr;//If asserted, a flit will be injected to ovc at next clk cycle
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assign ss_ovc_crossbar_wr = (ss_smart_chanel_new.requests[0] ) ? ss_smart_chanel_new.ovc : {V{1'b0}};
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assign ss_ovc_crossbar_wr = (ss_smart_chanel_new.requests[0] ) ? ss_smart_chanel_new.ovc : {V{1'b0}};
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| Line 867... |
Line 885... |
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end//for
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end//for
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endgenerate
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endgenerate
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register #(.W(1)) reg3 (.in(smart_chanel_i.hdr_flit), .reset(reset), .clk(clk), .out(smart_hdr_flit_req_o));
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pronoc_register #(.W(1)) reg3 (.in(smart_chanel_i.hdr_flit), .reset(reset), .clk(clk), .out(smart_hdr_flit_req_o));
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endmodule
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endmodule
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//
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//
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module smart_credit_manage #(
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module smart_credit_manage #(
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| Line 927... |
Line 945... |
else if(counter > 0) counter_next = counter -1'b1;
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else if(counter > 0) counter_next = counter -1'b1;
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end
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end
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assign credit_out = credit_in | smart_credit_in | (counter > 0);
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assign credit_out = credit_in | smart_credit_in | (counter > 0);
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register #(.W(Bw+1)) reg1 (.in(counter_next), .reset(reset), .clk(clk), .out(counter));
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pronoc_register #(.W(Bw+1)) reg1 (.in(counter_next), .reset(reset), .clk(clk), .out(counter));
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endmodule
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endmodule
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