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`timescale 1ns / 1ps
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`include "pronoc_def.v"
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/****************************************************************************
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/****************************************************************************
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* router_top.v
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* router_top.v
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****************************************************************************/
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****************************************************************************/
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Line 14... |
import pronoc_pkg::*;
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import pronoc_pkg::*;
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# (
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# (
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parameter P = 5 // router port num
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parameter P = 5 // router port num
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)(
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)(
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current_r_addr,// connected to constant parameter
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current_r_id,
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current_r_addr,
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chan_in,
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chan_in,
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chan_out,
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chan_out,
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router_event,
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clk,
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clk,
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reset
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reset
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);
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);
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localparam DISABLED =P;
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localparam DISABLED =P;
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input [RAw-1 : 0] current_r_addr;
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input [RAw-1 : 0] current_r_addr;
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input [31 : 0] current_r_id;
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input smartflit_chanel_t chan_in [P-1 : 0];
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input smartflit_chanel_t chan_in [P-1 : 0];
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output smartflit_chanel_t chan_out [P-1 : 0];
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output smartflit_chanel_t chan_out [P-1 : 0];
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output router_event_t router_event [P-1 : 0];
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input clk,reset;
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input clk,reset;
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genvar i,j;
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genvar i,j;
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Line 62... |
end
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end
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if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin
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if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin
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$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
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$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
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$finish;
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$finish;
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end
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end
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if(((SSA_EN=="YES") || (SMART_EN==1'b1) ) && CAST_TYPE!="UNICAST") begin
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$display("ERROR: SMART or SAA do not support muticast/braodcast packets");
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$finish;
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end
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end
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end
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/* verilator lint_on WIDTH */
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logic report_active_ivcs = 0;
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logic report_active_ivcs = 0;
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generate
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generate
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for (i=0; i
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for (i=0; i
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for (j=0; j
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for (j=0; j
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always @ (posedge report_active_ivcs) begin
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always @ (posedge report_active_ivcs) begin
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if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
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if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
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end
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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/* verilator lint_on WIDTH */
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//synopsys translate_on
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//synopsys translate_on
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//synthesis translate_on
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//synthesis translate_on
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generate
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for (i=0; i
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assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;
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assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;
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assign router_event[i].pck_wr_i = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;
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assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;
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assign router_event[i].pck_wr_o = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;
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assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;
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end
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endgenerate
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flit_chanel_t r2_chan_in [P-1 : 0];
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flit_chanel_t r2_chan_in [P-1 : 0];
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flit_chanel_t r2_chan_out [P-1 : 0];
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flit_chanel_t r2_chan_out [P-1 : 0];
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| Line 99... |
Line 128... |
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generate
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generate
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for (i=0; i
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for (i=0; i
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assign ctrl_in [i] = chan_in[i].ctrl_chanel;
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assign ctrl_in [i] = chan_in[i].ctrl_chanel;
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assign chan_out[i].ctrl_chanel= ctrl_out [i];
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assign chan_out[i].ctrl_chanel= ctrl_out [i];
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end
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end
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endgenerate
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endgenerate
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// synthesis translate_off
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// synthesis translate_off
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Line 171... |
.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
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.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
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.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
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.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
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.vc_num_in(chan_in[i].flit_chanel.flit.vc)
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.vc_num_in(chan_in[i].flit_chanel.flit.vc)
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);
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);
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check_pck_size #(
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.V(V),
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.MIN_PCK_SIZE(MIN_PCK_SIZE),
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.Fw(Fw),
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.DAw(DAw),
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.CAST_TYPE(CAST_TYPE),
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.NE(NE),
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.B(B),
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.LB(LB)
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)
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check_pck_siz
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(
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.clk(clk),
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.reset(reset),
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.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
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.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
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.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
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.vc_num_in(chan_in[i].flit_chanel.flit.vc),
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.dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
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);
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end
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end
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end
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end
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endgenerate
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endgenerate
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Line 216... |
.ovc_info (ovc_info),
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.ovc_info (ovc_info),
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.iport_info (iport_info),
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.iport_info (iport_info),
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.oport_info (oport_info),
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.oport_info (oport_info),
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.smart_ctrl_in (smart_ctrl),
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.smart_ctrl_in (smart_ctrl),
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.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.current_r_id(current_r_id),
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.chan_in (r2_chan_in),
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.chan_in (r2_chan_in),
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.chan_out (r2_chan_out),
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.chan_out (r2_chan_out),
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.ctrl_in (ctrl_in),
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.ctrl_in (ctrl_in),
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.ctrl_out (ctrl_out),
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.ctrl_out (ctrl_out),
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.clk (clk),
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.clk (clk),
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Line 322... |
.clk(clk)
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.clk(clk)
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);
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);
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// synthesis translate_on
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// synthesis translate_on
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assign smart_chanel_in[i] = chan_in[i].smart_chanel;
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assign smart_chanel_in[i] = chan_in[i].smart_chanel;
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assign chan_out[i].smart_chanel = smart_chanel_out[i];
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//r2 demux
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//r2 demux
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// flit_in_wr demux
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// flit_in_wr demux
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always @(*) begin
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always @(*) begin
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chan_out[i].smart_chanel = smart_chanel_out[i];
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chan_out[i].smart_chanel.flit_in_bypassed =smart_ctrl[i].smart_en & chan_in[i].flit_chanel.flit_wr ;
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//mask only flit_wr if smart_en is asserted
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//mask only flit_wr if smart_en is asserted
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r2_chan_in[i] = chan_in[i].flit_chanel;
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r2_chan_in[i] = chan_in[i].flit_chanel;
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//can replace destport here and remove lk rout from internal router
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//can replace destport here and remove lk rout from internal router
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if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
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if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
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//send flit_in to straight out port. Replace lk destport in header flit
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//send flit_in to straight out port. Replace lk destport in header flit
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ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
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ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
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if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] = smart_ctrl[i].lk_destport;
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if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] = smart_ctrl[i].lk_destport;
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end
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end
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Line 406... |
// //no output flit wr
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// //no output flit wr
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// if (r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;
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// if (r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;
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// end
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// end
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// if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
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// if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
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// end
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// end
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// register #( .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset), .clk(clk), .out (not_ideal));
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// pronoc_register #( .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset), .clk(clk), .out (not_ideal));
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//`endif
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//`endif
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endmodule
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endmodule
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| Line 364... |
Line 422... |
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# (
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# (
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parameter P = 5 // router port num
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parameter P = 5 // router port num
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)(
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)(
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current_r_addr,
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current_r_addr,
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current_r_id,
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chan_in,
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chan_in,
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chan_out,
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chan_out,
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router_event,
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clk,
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clk,
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reset
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reset
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);
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);
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input [RAw-1 : 0] current_r_addr;
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input [RAw-1 : 0] current_r_addr;
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input [31:0] current_r_id;
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input smartflit_chanel_t chan_in [P-1 : 0];
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input smartflit_chanel_t chan_in [P-1 : 0];
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output smartflit_chanel_t chan_out [P-1 : 0];
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output smartflit_chanel_t chan_out [P-1 : 0];
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input reset,clk;
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input reset,clk;
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output router_event_t router_event [P-1 : 0];
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router_top # (
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router_top # (
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.P(P)
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.P(P)
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)
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)
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router
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router
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(
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(
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.current_r_id(current_r_id),
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.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.chan_in (chan_in),
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.chan_in (chan_in),
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.chan_out(chan_out),
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.chan_out(chan_out),
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.router_event(router_event),
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.clk(clk),
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.clk(clk),
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.reset(reset)
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.reset(reset)
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);
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);
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