| Line 1... |
Line 1... |
`timescale 1ns/1ps
|
`include "pronoc_def.v"
|
|
|
//`define MONITORE_PATH
|
//`define MONITORE_PATH
|
|
|
/***********************************************************************
|
/***********************************************************************
|
** File: router.v
|
** File: router.v
|
| Line 34... |
Line 34... |
import pronoc_pkg::*;
|
import pronoc_pkg::*;
|
|
|
# (
|
# (
|
parameter P = 6 // router port num
|
parameter P = 6 // router port num
|
)(
|
)(
|
|
current_r_id,
|
current_r_addr,// connected to constant parameter
|
current_r_addr,// connected to constant parameter
|
|
|
chan_in,
|
chan_in,
|
chan_out,
|
chan_out,
|
|
|
| Line 62... |
Line 63... |
// The current/neighbor routers addresses/port. These values are fixed in each router and they are supposed to be given as parameter.
|
// The current/neighbor routers addresses/port. These values are fixed in each router and they are supposed to be given as parameter.
|
// However, in order to give an identical RTL code to each router, they are given as input ports. The identical RTL code reduces the
|
// However, in order to give an identical RTL code to each router, they are given as input ports. The identical RTL code reduces the
|
// compilation time. Note that they wont be implemented as input ports in the final synthesized code.
|
// compilation time. Note that they wont be implemented as input ports in the final synthesized code.
|
|
|
input [RAw-1 : 0] current_r_addr;
|
input [RAw-1 : 0] current_r_addr;
|
|
input [31:0] current_r_id;
|
|
|
input flit_chanel_t chan_in [P-1 : 0];
|
input flit_chanel_t chan_in [P-1 : 0];
|
output flit_chanel_t chan_out [P-1 : 0];
|
output flit_chanel_t chan_out [P-1 : 0];
|
input ctrl_chanel_t ctrl_in [P-1 : 0];
|
input ctrl_chanel_t ctrl_in [P-1 : 0];
|
output ctrl_chanel_t ctrl_out [P-1 : 0];
|
output ctrl_chanel_t ctrl_out [P-1 : 0];
|
| Line 95... |
Line 97... |
WP = W * P,
|
WP = W * P,
|
WPP= WP * P,
|
WPP= WP * P,
|
PRAw= P * RAw;
|
PRAw= P * RAw;
|
|
|
|
|
|
flit_chanel_t chan_in_tmp [P-1 : 0];
|
|
|
|
|
|
|
wire [PFw-1 : 0] flit_in_all;
|
wire [PFw-1 : 0] flit_in_all;
|
wire [P-1 : 0] flit_in_wr_all;
|
wire [P-1 : 0] flit_in_wr_all;
|
| Line 109... |
Line 111... |
wire [PFw-1 : 0] flit_out_all;
|
wire [PFw-1 : 0] flit_out_all;
|
wire [P-1 : 0] flit_out_wr_all;
|
wire [P-1 : 0] flit_out_wr_all;
|
wire [PV-1 : 0] credit_in_all;
|
wire [PV-1 : 0] credit_in_all;
|
wire [CONG_ALw-1 : 0] congestion_out_all;
|
wire [CONG_ALw-1 : 0] congestion_out_all;
|
|
|
|
wire [PV-1 : 0] credit_release_out;
|
|
|
|
|
// old router verilog code
|
// old router verilog code
|
|
|
|
|
| Line 136... |
Line 138... |
wire [PVP_1-1 : 0] dest_port_all;
|
wire [PVP_1-1 : 0] dest_port_all;
|
wire [PV-1 : 0] ovc_is_assigned_all;
|
wire [PV-1 : 0] ovc_is_assigned_all;
|
wire [PV-1 : 0] ivc_request_all;
|
wire [PV-1 : 0] ivc_request_all;
|
wire [PV-1 : 0] assigned_ovc_not_full_all;
|
wire [PV-1 : 0] assigned_ovc_not_full_all;
|
wire [PVV-1: 0] masked_ovc_request_all;
|
wire [PVV-1: 0] masked_ovc_request_all;
|
wire [PV-1 : 0] pck_is_single_flit_all;
|
|
wire [PV-1 : 0] vc_weight_is_consumed_all;
|
wire [PV-1 : 0] vc_weight_is_consumed_all;
|
wire [P-1 : 0] iport_weight_is_consumed_all;
|
wire [P-1 : 0] iport_weight_is_consumed_all;
|
wire [PV-1 : 0] vsa_ovc_released_all;
|
wire [PV-1 : 0] vsa_ovc_released_all;
|
wire [PV-1 : 0] vsa_credit_decreased_all;
|
wire [PV-1 : 0] vsa_credit_decreased_all;
|
|
|
// to/from the crossbar
|
// to/from the crossbar
|
wire [PFw-1 : 0] iport_flit_out_all;
|
wire [PFw-1 : 0] iport_flit_out_all;
|
wire [P-1 : 0] ssa_flit_wr_all;
|
wire [P-1 : 0] ssa_flit_wr_all;
|
reg [PP_1-1 : 0] granted_dest_port_all_delayed;
|
logic [PP_1-1 : 0] granted_dest_port_all_delayed;
|
wire [PFw-1 : 0] crossbar_flit_out_all;
|
wire [PFw-1 : 0] crossbar_flit_out_all;
|
wire [P-1 : 0] crossbar_flit_out_wr_all;
|
wire [P-1 : 0] crossbar_flit_out_wr_all;
|
wire [PFw-1 : 0] link_flit_out_all;
|
wire [PFw-1 : 0] link_flit_out_all;
|
wire [P-1 : 0] link_flit_out_wr_all;
|
wire [P-1 : 0] link_flit_out_wr_all;
|
wire [PV-1 : 0] flit_is_tail_all;
|
wire [PV-1 : 0] flit_is_tail_all;
|
| Line 166... |
Line 168... |
wire [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
|
wire [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
|
wire [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
|
wire [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
|
|
|
|
|
|
|
|
|
|
|
|
|
genvar i,j;
|
genvar i,j;
|
generate for (i=0; i
|
generate
|
|
for (i=0; i
|
|
|
|
if(CAST_TYPE == "UNICAST") begin : uni
|
|
assign chan_in_tmp[i] = chan_in[i];
|
|
end else begin : multi
|
|
multicast_chan_in_process #(
|
|
.P(P),
|
|
.SW_LOC (i)
|
|
) multicast_process (
|
|
.endp_port (ctrl_in[i].endp_port),
|
|
.current_r_addr (current_r_addr ),
|
|
.chan_in (chan_in[i] ),
|
|
.chan_out (chan_in_tmp[i] ),
|
|
.clk (clk)
|
|
);
|
|
|
|
end
|
|
|
|
|
assign neighbors_r_addr [(i+1)*RAw-1: i*RAw] = ctrl_in[i].neighbors_r_addr;
|
assign neighbors_r_addr [(i+1)*RAw-1: i*RAw] = ctrl_in[i].neighbors_r_addr;
|
assign flit_in_all [(i+1)*Fw-1: i*Fw] = chan_in[i].flit;
|
assign flit_in_all [(i+1)*Fw-1: i*Fw] = chan_in_tmp[i].flit;
|
assign flit_in_wr_all [i] = chan_in[i].flit_wr;
|
assign flit_in_wr_all [i] = chan_in_tmp[i].flit_wr;
|
assign credit_in_all [(i+1)*V-1: i*V] = chan_in[i].credit;
|
assign credit_in_all [(i+1)*V-1: i*V] = chan_in_tmp[i].credit;
|
assign congestion_in_all [(i+1)*CONGw-1: i*CONGw] = chan_in[i].congestion;
|
assign congestion_in_all [(i+1)*CONGw-1: i*CONGw] = chan_in_tmp[i].congestion;
|
|
|
assign ctrl_out[i].neighbors_r_addr = current_r_addr;
|
assign ctrl_out[i].neighbors_r_addr = current_r_addr;
|
|
assign ctrl_out[i].endp_port =1'b0;
|
|
|
|
|
assign chan_out[i].flit= flit_out_all [(i+1)*Fw-1: i*Fw];
|
assign chan_out[i].flit= flit_out_all [(i+1)*Fw-1: i*Fw];
|
assign chan_out[i].flit_wr= flit_out_wr_all [i];
|
assign chan_out[i].flit_wr= flit_out_wr_all [i];
|
assign chan_out[i].credit= credit_out_all [(i+1)*V-1: i*V];
|
assign chan_out[i].credit= credit_out_all [(i+1)*V-1: i*V] | credit_release_out [(i+1)*V-1: i*V];
|
assign chan_out[i].congestion= congestion_out_all [(i+1)*CONGw-1: i*CONGw];
|
assign chan_out[i].congestion= congestion_out_all [(i+1)*CONGw-1: i*CONGw];
|
|
|
|
|
assign iport_info[i].swa_first_level_grant =nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1: i*V];
|
assign iport_info[i].swa_first_level_grant =nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1: i*V];
|
assign iport_info[i].swa_grant = ivc_num_getting_sw_grant[(i+1)*V-1: i*V];
|
assign iport_info[i].swa_grant = ivc_num_getting_sw_grant[(i+1)*V-1: i*V];
|
assign iport_info[i].any_ivc_get_swa_grant= any_ivc_sw_request_granted_all[i];
|
assign iport_info[i].any_ivc_get_swa_grant= any_ivc_sw_request_granted_all[i];
|
assign iport_info[i].ivc_req = ivc_request_all [(i+1)*V-1: i*V];
|
assign iport_info[i].ivc_req = ivc_request_all [(i+1)*V-1: i*V];
|
|
|
| Line 207... |
Line 235... |
end else begin :slp
|
end else begin :slp
|
assign iport_info[i].granted_oport_one_hot[P-1 : 0] = granted_dest_port_all[(i+1)*P_1-1: i*P_1];
|
assign iport_info[i].granted_oport_one_hot[P-1 : 0] = granted_dest_port_all[(i+1)*P_1-1: i*P_1];
|
end
|
end
|
|
|
for (j=0;j
|
for (j=0;j
|
|
|
|
//credit_release. Only activated for local ports as credit_release_en never be asserted in router to router connection.
|
|
credit_release_gen #(
|
|
.CREDIT_NUM (LB)
|
|
) credit_release_gen (
|
|
.clk (clk ),
|
|
.reset (reset ),
|
|
.en (ctrl_in[i].credit_release_en[j] ),
|
|
.credit_out (credit_release_out[i*V+j] )
|
|
);
|
|
|
|
|
|
assign ctrl_out[i].credit_release_en[j] =1'b0;
|
assign credit_init_val_in[i][j] = ctrl_in[i].credit_init_val[j];
|
assign credit_init_val_in[i][j] = ctrl_in[i].credit_init_val[j];
|
assign ctrl_out[i].credit_init_val[j] = credit_init_val_out [i][j];
|
assign ctrl_out[i].credit_init_val[j] = credit_init_val_out [i][j];
|
|
|
|
|
|
|
|
|
end
|
end
|
|
|
|
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 230... |
Line 277... |
.flit_in_all(flit_in_all),
|
.flit_in_all(flit_in_all),
|
.flit_in_wr_all(flit_in_wr_all),
|
.flit_in_wr_all(flit_in_wr_all),
|
.credit_out_all(credit_out_all),
|
.credit_out_all(credit_out_all),
|
.credit_in_all(credit_in_all),
|
.credit_in_all(credit_in_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.pck_is_single_flit_all(pck_is_single_flit_all),
|
|
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
|
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
|
.vsa_ovc_allocated_all(ovc_allocated_all),
|
.vsa_ovc_allocated_all(ovc_allocated_all),
|
.granted_ovc_num_all(granted_ovc_num_all),
|
.granted_ovc_num_all(granted_ovc_num_all),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.spec_ovc_num_all(spec_ovc_num_all),
|
.spec_ovc_num_all(spec_ovc_num_all),
|
| Line 274... |
Line 320... |
.vsa_credit_decreased_all(vsa_credit_decreased_all)
|
.vsa_credit_decreased_all(vsa_credit_decreased_all)
|
);
|
);
|
|
|
|
|
combined_vc_sw_alloc #(
|
combined_vc_sw_alloc #(
|
.V(V),
|
.P(P)
|
.P(P),
|
|
.COMBINATION_TYPE(COMBINATION_TYPE),
|
|
.FIRST_ARBITER_EXT_P_EN (FIRST_ARBITER_EXT_P_EN),
|
|
.SWA_ARBITER_TYPE (SWA_ARBITER_TYPE ),
|
|
.DEBUG_EN(DEBUG_EN),
|
|
.MIN_PCK_SIZE(MIN_PCK_SIZE),
|
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
|
)
|
)
|
vsa
|
vsa
|
(
|
(
|
.dest_port_all(dest_port_all),
|
.dest_port_all(dest_port_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
|
.ivc_request_all(ivc_request_all),
|
|
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
|
|
.pck_is_single_flit_all(pck_is_single_flit_all),
|
|
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
|
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
|
.ovc_allocated_all(ovc_allocated_all),
|
.ovc_allocated_all(ovc_allocated_all),
|
.granted_ovc_num_all(granted_ovc_num_all),
|
.granted_ovc_num_all(granted_ovc_num_all),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
|
| Line 307... |
Line 342... |
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
|
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
|
.spec_ovc_num_all(spec_ovc_num_all),
|
.spec_ovc_num_all(spec_ovc_num_all),
|
// .lk_destination_all(lk_destination_all),
|
// .lk_destination_all(lk_destination_all),
|
.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
|
.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
|
.iport_weight_is_consumed_all(iport_weight_is_consumed_all),
|
.iport_weight_is_consumed_all(iport_weight_is_consumed_all),
|
|
.ivc_info(ivc_info),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
|
|
|
pronoc_register #(.W(PP_1)) reg2 (.in(granted_dest_port_all ), .out(granted_dest_port_all_delayed), .reset(reset), .clk(clk));
|
|
|
|
|
|
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset) begin
|
|
granted_dest_port_all_delayed<= {PP_1{1'b0}};
|
|
end else begin
|
|
granted_dest_port_all_delayed<= granted_dest_port_all;
|
|
end
|
|
end//always
|
|
|
|
crossbar #(
|
crossbar #(
|
|
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.V (V), // vc_num_per_port
|
.V (V), // vc_num_per_port
|
.P (P), // router port num
|
.P (P), // router port num
|
| Line 357... |
Line 380... |
|
|
|
|
reg [PFw-1 : 0] flit_out_all_pipe;
|
reg [PFw-1 : 0] flit_out_all_pipe;
|
reg [P-1 : 0] flit_out_wr_all_pipe;
|
reg [P-1 : 0] flit_out_wr_all_pipe;
|
|
|
`ifdef SYNC_RESET_MODE
|
pronoc_register #(.W(PFw)) reg1 (.in(crossbar_flit_out_all ), .out(flit_out_all_pipe), .reset(reset), .clk(clk));
|
always @ (posedge clk )begin
|
pronoc_register #(.W(P) ) reg2 (.in(crossbar_flit_out_wr_all ), .out(flit_out_wr_all_pipe), .reset(reset), .clk(clk));
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset)begin
|
|
flit_out_all_pipe <= {PFw{1'b0}};
|
|
flit_out_wr_all_pipe <= {P{1'b0}};
|
|
end else begin
|
|
flit_out_all_pipe <= crossbar_flit_out_all;
|
|
flit_out_wr_all_pipe <= crossbar_flit_out_wr_all;
|
|
end
|
|
end
|
|
|
|
assign link_flit_out_all = flit_out_all_pipe;
|
assign link_flit_out_all = flit_out_all_pipe;
|
assign link_flit_out_wr_all = flit_out_wr_all_pipe;
|
assign link_flit_out_wr_all = flit_out_wr_all_pipe;
|
|
|
|
|
| Line 491... |
Line 504... |
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(reset)begin
|
if(reset)begin
|
t1[i]<=1'b0;
|
t1[i]<=1'b0;
|
t2[i]<=1'b0;
|
t2[i]<=1'b0;
|
end else begin
|
end else begin
|
if(flit_in_wr_all[i]>0 && t1[i]==0)begin
|
|
$display("%t :In router (addr=%h, port=%d), flitin=%h",$time,current_r_addr,i,flit_in_all[(i+1)*Fw-1 : i*Fw]);
|
|
t1[i]<=1;
|
|
end
|
|
if(flit_out_wr_all[i]>0 && t2[i]==0)begin
|
if(flit_out_wr_all[i]>0 && t2[i]==0)begin
|
$display("%t :Out router (addr=%h, port=%d), flitout=%h",$time,current_r_addr,i,flit_out_all[(i+1)*Fw-1 : i*Fw]);
|
$display("%t :Out router (id=%d, addr=%h, port=%d), flitout=%h",$time,current_r_id,current_r_addr,i,flit_out_all[(i+1)*Fw-1 : i*Fw]);
|
t2[i]<=1;
|
t2[i]<=1;
|
end
|
end
|
|
|
|
if(flit_in_wr_all[i]>0 && t1[i]==0)begin
|
|
$display("%t :In router (id=%d, addr=%h, port=%d), flitin=%h",$time,current_r_id,current_r_addr,i,flit_in_all[(i+1)*Fw-1 : i*Fw]);
|
|
t1[i]<=1;
|
|
end
|
|
|
|
|
|
|
end
|
end
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
| Line 516... |
Line 531... |
|
|
|
|
reg [10 : 0] counter;
|
reg [10 : 0] counter;
|
reg [31 : 0] flit_counter;
|
reg [31 : 0] flit_counter;
|
|
|
always @(posedge clk or posedge reset) begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if(reset) begin
|
if(`pronoc_reset) begin
|
flit_counter <=0;
|
flit_counter <=0;
|
counter <= 0;
|
counter <= 0;
|
end else begin
|
end else begin
|
if(flit_in_wr_all>0 )begin
|
if(flit_in_wr_all>0 )begin
|
counter <=0;
|
counter <=0;
|
| Line 540... |
Line 555... |
//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
module credit_release_gen
|
|
import pronoc_pkg::*;
|
|
#(
|
|
parameter CREDIT_NUM=4
|
|
)(
|
|
clk,
|
|
reset,
|
|
en,
|
|
credit_out
|
|
);
|
|
input clk, reset;
|
|
input en;
|
|
output reg credit_out;
|
|
|
|
localparam W=log2(CREDIT_NUM +1);
|
|
|
|
reg [W-1 : 0] counter;
|
|
wire counter_is_zero = counter=={W{1'b0}};
|
|
wire counter_is_max = counter==CREDIT_NUM;
|
|
wire counter_incr = (en & counter_is_zero ) | (~counter_is_zero & ~counter_is_max);
|
|
|
|
|
|
|
|
|
|
always @ (`pronoc_clk_reset_edge )begin
|
|
if(`pronoc_reset) begin
|
|
counter <= {W{1'b0}};
|
|
credit_out<=1'b0;
|
|
end else begin
|
|
if(counter_incr) begin
|
|
counter<= counter +1'b1;
|
|
credit_out<=1'b1;
|
|
end else begin
|
|
credit_out<=1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
endmodule
|
|
|
