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`timescale 1ns / 1ps
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`include "pronoc_def.v"
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/**********************************************************************
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/**********************************************************************
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** File: ss_allocator.v
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** File: ss_allocator.v
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** Date:2016-06-19
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** Date:2016-06-19
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**
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**
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flit_in_wr_all,
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flit_in_wr_all,
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flit_in_all,
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flit_in_all,
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any_ovc_granted_in_outport_all ,
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any_ovc_granted_in_outport_all ,
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any_ivc_sw_request_granted_all ,
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any_ivc_sw_request_granted_all ,
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ovc_avalable_all,
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ovc_avalable_all,
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assigned_ovc_not_full_all,
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// assigned_ovc_not_full_all,
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ivc_request_all,
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// dest_port_encoded_all,
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dest_port_encoded_all,
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// assigned_ovc_num_all,
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assigned_ovc_num_all,
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// ovc_is_assigned_all,
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ovc_is_assigned_all,
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ivc_info,
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ssa_ctrl_o
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ssa_ctrl_o
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);
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);
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localparam PV = V * P,
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localparam PV = V * P,
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input [PFw-1 : 0] flit_in_all;
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input [PFw-1 : 0] flit_in_all;
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input [P-1 : 0] flit_in_wr_all;
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input [P-1 : 0] flit_in_wr_all;
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input [P-1 : 0] any_ovc_granted_in_outport_all;
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input [P-1 : 0] any_ovc_granted_in_outport_all;
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input [P-1 : 0] any_ivc_sw_request_granted_all;
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input [P-1 : 0] any_ivc_sw_request_granted_all;
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input [PV-1 : 0] ovc_avalable_all;
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input [PV-1 : 0] ovc_avalable_all;
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input [PV-1 : 0] assigned_ovc_not_full_all;
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input [PV-1 : 0] ivc_request_all;
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input [PVDSTPw-1 : 0] dest_port_encoded_all;
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input [PVV-1 : 0] assigned_ovc_num_all;
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input [PV-1 : 0] ovc_is_assigned_all;
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input reset,clk;
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input reset,clk;
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input ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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output ssa_ctrl_t ssa_ctrl_o [P-1 : 0];
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output ssa_ctrl_t ssa_ctrl_o [P-1 : 0];
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wire [PV-1 : 0] ovc_allocated_all;
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wire [PV-1 : 0] ovc_allocated_all;
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wire [PV-1 : 0] ovc_released_all;
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wire [PV-1 : 0] ovc_released_all;
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wire [PV-1 : 0] ivc_num_getting_sw_grant_all;
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wire [PV-1 : 0] ivc_num_getting_sw_grant_all;
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wire [PV-1 : 0] ivc_num_getting_ovc_grant_all;
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wire [PV-1 : 0] ivc_num_getting_ovc_grant_all;
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wire [PV-1 : 0] ivc_reset_all;
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wire [PV-1 : 0] ivc_reset_all;
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wire [PV-1 : 0] single_flit_pck_all,ovc_single_flit_pck_all;
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wire [PV-1 : 0] single_flit_pck_all,ovc_single_flit_pck_all;
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wire [PV-1 : 0] decreased_credit_in_ss_ovc_all;
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wire [PV-1 : 0] decreased_credit_in_ss_ovc_all;
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reg [P-1 : 0] ssa_flit_wr_all;
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wire [P-1 : 0] ssa_flit_wr_all;
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wire [PV-1 : 0] any_ovc_granted_in_ss_port;
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wire [PV-1 : 0] any_ovc_granted_in_ss_port;
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wire [PV-1 : 0] ovc_avalable_in_ss_port;
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wire [PV-1 : 0] ovc_avalable_in_ss_port;
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wire [PV-1 : 0] ovc_allocated_in_ss_port;
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wire [PV-1 : 0] ovc_allocated_in_ss_port;
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wire [PV-1 : 0] ovc_released_in_ss_port;
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wire [PV-1 : 0] ovc_released_in_ss_port;
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wire [PV-1 : 0] decreased_credit_in_ss_ovc;
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wire [PV-1 : 0] decreased_credit_in_ss_ovc;
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wire [PV-1 : 0] ivc_num_getting_sw_grantin_SS_all;
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wire [PV-1 : 0] ivc_num_getting_sw_grantin_SS_all;
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wire [PV-1 : 0] ivc_request_all;
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wire [PV-1 : 0] assigned_ovc_not_full_all;
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wire [PVDSTPw-1 : 0] dest_port_encoded_all;
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wire [PVV-1 : 0] assigned_ovc_num_all;
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wire [PV-1 : 0] ovc_is_assigned_all;
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genvar i;
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genvar i;
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// there is no ssa for local port in 5 and 3 port routers
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// there is no ssa for local port in 5 and 3 port routers
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generate
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generate
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for (i=0; i
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for (i=0; i
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localparam C_PORT = i/V;
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localparam C_PORT = i/V;
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localparam SS_PORT = strieght_port (P,C_PORT);
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localparam SS_PORT = strieght_port (P,C_PORT);
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assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
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assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
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assign dest_port_encoded_all [(i+1)*DSTPw-1 : i*DSTPw] = ivc_info[C_PORT][i%V].dest_port_encoded;
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assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[C_PORT][i%V].assigned_ovc_num;
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assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
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if (SS_PORT == DISABLED)begin : no_prefrable
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if (SS_PORT == DISABLED)begin : no_prefrable
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assign ovc_allocated_all[i]= 1'b0;
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assign ovc_allocated_all[i]= 1'b0;
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assign ovc_released_all [i]= 1'b0;
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assign ovc_released_all [i]= 1'b0;
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end//ssa
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end//ssa
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end// vc_loop
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end// vc_loop
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for(i=0;i
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for(i=0;i
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`ifdef SYNC_RESET_MODE
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always @ (posedge clk )begin
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`else
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pronoc_register #(.W(1)) reg1 (
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always @ (posedge clk or posedge reset)begin
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.in(|ivc_num_getting_sw_grantin_SS_all[(i+1)*V-1 : i*V] ),
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`endif
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.out(ssa_flit_wr_all[i]),
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if(reset)begin
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.reset(reset),
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ssa_flit_wr_all[i]<=1'b0;
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.clk(clk));
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end else begin
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ssa_flit_wr_all[i]<= |ivc_num_getting_sw_grantin_SS_all[(i+1)*V-1 : i*V];
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end //reset
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end// always
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assign ssa_ctrl_o[i].ovc_is_allocated =ovc_allocated_all [(i+1)*V-1 : i*V];
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assign ssa_ctrl_o[i].ovc_is_allocated =ovc_allocated_all [(i+1)*V-1 : i*V];
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assign ssa_ctrl_o[i].ovc_is_released = ovc_released_all [(i+1)*V-1 : i*V];
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assign ssa_ctrl_o[i].ovc_is_released = ovc_released_all [(i+1)*V-1 : i*V];
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