| Line 1... |
Line 1... |
`timescale 1ns/1ps
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`include "pronoc_def.v"
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module traffic_gen_top
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module traffic_gen_top
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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#(
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#(
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parameter MAX_RATIO = 1000,
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parameter MAX_RATIO = 1000,
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| Line 37... |
Line 37... |
distance,
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distance,
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pck_class_out,
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pck_class_out,
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time_stamp_h2h,
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time_stamp_h2h,
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time_stamp_h2t,
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time_stamp_h2t,
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pck_size_o,
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pck_size_o,
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mcast_dst_num_o,
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reset,
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reset,
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clk
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clk
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);
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);
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| Line 76... |
Line 77... |
output [Cw-1 :0] pck_class_out;
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output [Cw-1 :0] pck_class_out;
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// the current endpoint address
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// the current endpoint address
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input [EAw-1 :0] current_e_addr;
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input [EAw-1 :0] current_e_addr;
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// the destination endpoint address
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// the destination endpoint address
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input [EAw-1 :0] dest_e_addr;
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input [DAw-1 :0] dest_e_addr;
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output [PCK_CNTw-1 :0] pck_number;
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output [PCK_CNTw-1 :0] pck_number;
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input [PCK_SIZw-1 :0] pck_size_in;
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input [PCK_SIZw-1 :0] pck_size_in;
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output reg sent_done;
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output reg sent_done;
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| Line 91... |
Line 92... |
input report;
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input report;
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input [DELAYw-1 :0] start_delay;
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input [DELAYw-1 :0] start_delay;
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// the received packet source endpoint address
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// the received packet source endpoint address
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output [EAw-1 : 0] src_e_addr;
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output [EAw-1 : 0] src_e_addr;
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output [PCK_SIZw-1 : 0] pck_size_o;
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output [PCK_SIZw-1 : 0] pck_size_o;
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output [NEw-1 : 0] mcast_dst_num_o;
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logic [Fw-1 :0] flit_out;
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logic [Fw-1 :0] flit_out;
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output logic flit_out_wr;
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output logic flit_out_wr;
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output [Cw-1 : 0] flit_out_class;
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output [Cw-1 : 0] flit_out_class;
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| Line 106... |
Line 108... |
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// the connected router address
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// the connected router address
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wire [RAw-1 :0] current_r_addr;
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wire [RAw-1 :0] current_r_addr;
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/* verilator lint_off WIDTH */
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wire [PCK_SIZw-1 : 0] pck_size_tmp= (PCK_TYPE == "SINGLE_FLIT" )? 1 : pck_size_in;
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/* verilator lint_on WIDTH */
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assign chan_out.flit_chanel.flit = flit_out;
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assign chan_out.flit_chanel.flit = flit_out;
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assign chan_out.flit_chanel.flit_wr = flit_out_wr;
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assign chan_out.flit_chanel.flit_wr = flit_out_wr;
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assign chan_out.flit_chanel.credit = credit_out;
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assign chan_out.flit_chanel.credit = credit_out;
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assign chan_out.smart_chanel = {SMART_CHANEL_w {1'b0}};
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assign flit_in = chan_in.flit_chanel.flit;
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assign flit_in = chan_in.flit_chanel.flit;
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assign flit_in_wr= chan_in.flit_chanel.flit_wr;
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assign flit_in_wr= chan_in.flit_chanel.flit_wr;
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assign credit_in = chan_in.flit_chanel.credit;
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assign credit_in = chan_in.flit_chanel.credit;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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| Line 123... |
Line 129... |
for (i=0; i
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for (i=0; i
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assign chan_out.ctrl_chanel.credit_init_val[i]= PORT_B;
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assign chan_out.ctrl_chanel.credit_init_val[i]= PORT_B;
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end
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end
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endgenerate
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endgenerate
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assign chan_out.ctrl_chanel.endp_port =1'b1;
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assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
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//old traffic.v file
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//old traffic.v file
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reg [2:0] ps,ns;
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reg [2:0] ps,ns;
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localparam IDEAL =3'b001, SENT =3'b010, WAIT=3'b100;
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localparam IDEAL =3'b001, SENT =3'b010, WAIT=3'b100;
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reg inject_en,cand_wr_vc_en,pck_rd;
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reg inject_en,cand_wr_vc_en,pck_rd;
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reg [PCK_SIZw-1 :0] pck_size, pck_size_next;
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reg [PCK_SIZw-1 :0] pck_size;
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reg [EAw-1 :0] dest_e_addr_reg;
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logic [DAw-1 :0] dest_e_addr_reg,dest_e_addr_o;
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// synopsys translate_off
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// synopsys translate_off
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// synthesis translate_off
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// synthesis translate_off
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`ifdef MONITORE_PATH
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`ifdef MONITORE_PATH
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| Line 165... |
Line 174... |
HDR_DATA_w = (MIN_PCK_SIZE==1)? CLK_CNTw : 0,
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HDR_DATA_w = (MIN_PCK_SIZE==1)? CLK_CNTw : 0,
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HDR_Dw = (MIN_PCK_SIZE==1)? CLK_CNTw : 1;
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HDR_Dw = (MIN_PCK_SIZE==1)? CLK_CNTw : 1;
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wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;
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wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;
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pronoc_register #(.W(DAw)) reg2 (.in(dest_e_addr ), .out(dest_e_addr_reg), .reset(reset), .clk(clk));
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`ifdef SYNC_RESET_MODE
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always @ (posedge clk )begin
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`else
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always @ (posedge clk or posedge reset)begin
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`endif
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if(reset) begin
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dest_e_addr_reg<={EAw{1'b0}};
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end else begin
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dest_e_addr_reg<=dest_e_addr;
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end
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end
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wire [DSTPw-1 : 0] destport;
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wire [DSTPw-1 : 0] destport;
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wire [V-1 : 0] ovc_wr_in;
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wire [V-1 : 0] ovc_wr_in;
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wire [V-1 : 0] full_vc,empty_vc,nearly_full_vc;
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wire [V-1 : 0] full_vc,empty_vc,nearly_full_vc;
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reg [V-1 : 0] wr_vc,wr_vc_next;
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reg [V-1 : 0] wr_vc,wr_vc_next;
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| Line 192... |
Line 192... |
reg [PCK_SIZw-1 : 0] flit_counter;
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reg [PCK_SIZw-1 : 0] flit_counter;
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reg flit_cnt_rst,flit_cnt_inc;
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reg flit_cnt_rst,flit_cnt_inc;
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wire rd_hdr_flg,rd_tail_flg;
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wire rd_hdr_flg,rd_tail_flg;
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wire [Cw-1 : 0] rd_class_hdr;
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wire [Cw-1 : 0] rd_class_hdr;
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// wire [P_1-1 : 0] rd_destport_hdr;
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// wire [P_1-1 : 0] rd_destport_hdr;
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wire [EAw-1 : 0] rd_des_e_addr, rd_src_e_addr;
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wire [DAw-1 : 0] rd_des_e_addr;
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wire [EAw-1 : 0] rd_src_e_addr;
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reg [CLK_CNTw-1 : 0] rsv_counter;
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reg [CLK_CNTw-1 : 0] rsv_counter;
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reg [CLK_CNTw-1 : 0] clk_counter;
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reg [CLK_CNTw-1 : 0] clk_counter;
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wire [Vw-1 : 0] rd_vc_bin;//,wr_vc_bin;
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wire [Vw-1 : 0] rd_vc_bin;//,wr_vc_bin;
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reg [CLK_CNTw-1 : 0] rsv_time_stamp[V-1:0];
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reg [CLK_CNTw-1 : 0] rsv_time_stamp[V-1:0];
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reg [PCK_SIZw-1 : 0] rsv_pck_size [V-1:0];
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reg [PCK_SIZw-1 : 0] rsv_pck_size [V-1:0];
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| Line 213... |
Line 215... |
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logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
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logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
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logic start_en_next , start_en;
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logic start_en_next , start_en;
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register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );
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pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );
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register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );
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pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );
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always @(*) begin
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always @(*) begin
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start_en_next =start_en;
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start_en_next =start_en;
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| Line 243... |
Line 245... |
.TOPOLOGY(TOPOLOGY),
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.TOPOLOGY(TOPOLOGY),
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.T1(T1),
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.T1(T1),
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.T2(T2),
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.T2(T2),
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.T3(T3),
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.T3(T3),
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.EAw(EAw),
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.EAw(EAw),
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.SELF_LOOP_EN(SELF_LOOP_EN)
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.SELF_LOOP_EN(SELF_LOOP_EN),
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.DAw(DAw),
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.CAST_TYPE(CAST_TYPE),
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.NE(NE)
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)
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)
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check_destination_addr(
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check_destination_addr(
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.dest_e_addr(dest_e_addr),
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.dest_e_addr(dest_e_addr),
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.current_e_addr(current_e_addr),
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.current_e_addr(current_e_addr),
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.dest_is_valid(valid_dst)
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.dest_is_valid(valid_dst)
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| Line 263... |
Line 268... |
.MAX_RATIO(MAX_RATIO)
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.MAX_RATIO(MAX_RATIO)
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)
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)
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pck_inject_ratio_ctrl
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pck_inject_ratio_ctrl
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(
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(
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.en(inject_en),
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.en(inject_en),
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.pck_size_in(pck_size_in),
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.pck_size_in(pck_size_tmp),
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.freez(buffer_full),
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.freez(buffer_full),
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.inject(pck_wr),
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.inject(pck_wr),
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.ratio(ratio)
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.ratio(ratio)
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| Line 294... |
Line 299... |
.reset (reset)
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.reset (reset)
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);
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);
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packet_gen #(
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packet_gen #(
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.P(MAX_P),
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.P(MAX_P),
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.T1(T1),
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.PCK_TYPE(PCK_TYPE),
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.T2(T2),
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.T3(T3),
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.RAw(RAw),
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.EAw(EAw),
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.TOPOLOGY(TOPOLOGY),
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.DSTPw(DSTPw),
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.ROUTE_NAME(ROUTE_NAME),
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.ROUTE_TYPE(ROUTE_TYPE),
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.ROUTE_TYPE(ROUTE_TYPE),
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.MAX_PCK_NUM(MAX_PCK_NUM),
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.MAX_PCK_NUM(MAX_PCK_NUM),
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.MAX_SIM_CLKs(MAX_SIM_CLKs),
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.MAX_SIM_CLKs(MAX_SIM_CLKs),
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.TIMSTMP_FIFO_NUM(TIMSTMP_FIFO_NUM),
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.TIMSTMP_FIFO_NUM(TIMSTMP_FIFO_NUM),
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.MIN_PCK_SIZE(MIN_PCK_SIZE),
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.MIN_PCK_SIZE(MIN_PCK_SIZE),
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| Line 321... |
Line 320... |
.pck_rd(pck_rd),
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.pck_rd(pck_rd),
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.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.current_e_addr(current_e_addr),
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.current_e_addr(current_e_addr),
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.clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
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.clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
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.pck_number(pck_number),
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.pck_number(pck_number),
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.dest_e_addr(dest_e_addr_reg),
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.dest_e_addr_in(dest_e_addr),
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.dest_e_addr_o(dest_e_addr_o),
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.pck_timestamp(pck_timestamp),
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.pck_timestamp(pck_timestamp),
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.buffer_full(buffer_full),
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.buffer_full(buffer_full),
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.pck_ready(pck_ready),
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.pck_ready(pck_ready),
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.valid_dst(valid_dst),
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.valid_dst(valid_dst),
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.destport(destport),
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.destport(destport),
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.pck_size_in(pck_size_in),
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.pck_size_in(pck_size_tmp),
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.pck_size_o(pck_size)
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.pck_size_o(pck_size)
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);
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);
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assign wr_timestamp =pck_timestamp;
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assign wr_timestamp =pck_timestamp;
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assign update = flit_in_wr & flit_in[Fw-2];
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assign update = flit_in_wr & flit_in[Fw-2];
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assign hdr_flit = (flit_counter == 0);
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assign hdr_flit = (flit_counter == 0);
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assign tail_flit = (flit_counter == pck_size-1'b1);
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assign tail_flit = (flit_counter == pck_size-1'b1);
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| Line 364... |
Line 367... |
the_header_flit_generator
|
the_header_flit_generator
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(
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(
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.flit_out(hdr_flit_out),
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.flit_out(hdr_flit_out),
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.vc_num_in(wr_vc),
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.vc_num_in(wr_vc),
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.class_in(pck_class_in),
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.class_in(pck_class_in),
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.dest_e_addr_in(dest_e_addr_reg),
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.dest_e_addr_in(dest_e_addr_o),
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.src_e_addr_in(current_e_addr),
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.src_e_addr_in(current_e_addr),
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.weight_in(init_weight),
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.weight_in(init_weight),
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.destport_in(destport),
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.destport_in(destport),
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.data_in(hdr_data_in),
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.data_in(hdr_data_in),
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.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
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.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
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| Line 567... |
Line 570... |
if(flit_in_wr) begin
|
if(flit_in_wr) begin
|
credit_out_next = rd_vc;
|
credit_out_next = rd_vc;
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end else credit_out_next = {V{1'd0}};
|
end else credit_out_next = {V{1'd0}};
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end
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end
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always @ (*)begin
|
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pck_size_next = pck_size;
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if((tail_flit & flit_out_wr ) || not_yet_sent_aflit) pck_size_next = pck_size_in;
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end
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`ifdef SYNC_RESET_MODE
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always @ (`pronoc_clk_reset_edge )begin
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always @ (posedge clk )begin
|
if(`pronoc_reset) begin
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`else
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always @ (posedge clk or posedge reset)begin
|
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`endif
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if(reset) begin
|
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inject_en <= 1'b0;
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inject_en <= 1'b0;
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ps <= IDEAL;
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ps <= IDEAL;
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wr_vc <=1;
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wr_vc <=1;
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flit_counter <= {PCK_SIZw{1'b0}};
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flit_counter <= {PCK_SIZw{1'b0}};
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credit_out <= {V{1'd0}};
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credit_out <= {V{1'd0}};
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rsv_counter <= 0;
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rsv_counter <= 0;
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clk_counter <= 0;
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clk_counter <= 0;
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//pck_size <= 0;
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not_yet_sent_aflit<=1'b1;
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not_yet_sent_aflit<=1'b1;
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end else begin
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end else begin
|
//injection
|
//injection
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not_yet_sent_aflit<=not_yet_sent_aflit_next;
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not_yet_sent_aflit<=not_yet_sent_aflit_next;
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| Line 598... |
Line 592... |
clk_counter <= clk_counter+1'b1;
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clk_counter <= clk_counter+1'b1;
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wr_vc <=wr_vc_next;
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wr_vc <=wr_vc_next;
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if (flit_cnt_rst) flit_counter <= {PCK_SIZw{1'b0}};
|
if (flit_cnt_rst) flit_counter <= {PCK_SIZw{1'b0}};
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else if(flit_cnt_inc) flit_counter <= flit_counter + 1'b1;
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else if(flit_cnt_inc) flit_counter <= flit_counter + 1'b1;
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credit_out <= credit_out_next;
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credit_out <= credit_out_next;
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//pck_size <= pck_size_next;
|
|
|
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//sink
|
//sink
|
if(flit_in_wr) begin
|
if(flit_in_wr) begin
|
if (flit_in[Fw-1])begin //header flit
|
if (flit_in[Fw-1])begin //header flit
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rsv_pck_src_e_addr[rd_vc_bin] <= rd_src_e_addr;
|
rsv_pck_src_e_addr[rd_vc_bin] <= rd_src_e_addr;
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| Line 637... |
Line 631... |
|
|
end
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end
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end//always
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end//always
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// synopsys translate_off
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|
|
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|
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wire [NE-1 :0] dest_mcast_all_endp1;
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|
|
|
|
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generate
|
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/* verilator lint_off WIDTH */
|
|
if(CAST_TYPE != "UNICAST") begin :mb_cast
|
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/* verilator lint_on WIDTH */
|
|
|
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wire [NEw-1 : 0] sum_temp;
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wire is_unicast;
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|
|
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mcast_dest_list_decode decode1 (
|
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.dest_e_addr(dest_e_addr_o),
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.dest_o(dest_mcast_all_endp1),
|
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.row_has_any_dest(),
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.is_unicast(is_unicast)
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|
);
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|
|
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/* verilator lint_off WIDTH */
|
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if (CAST_TYPE == "BROADCAST_FULL") begin :bcastf
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assign mcast_dst_num_o = (is_unicast) ? 1 : (SELF_LOOP_EN == "NO")? NE-1 : NE;
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|
end else if ( CAST_TYPE == "BROADCAST_PARTIAL" ) begin :bcastp
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|
|
|
if (SELF_LOOP_EN == "NO") begin
|
|
//check if injector node is included in partial list
|
|
wire [NEw-1: 0] current_enp_id;
|
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod1 ( .id(current_enp_id), .code(current_e_addr));
|
|
assign mcast_dst_num_o = (is_unicast) ? 1 : (MCAST_ENDP_LIST[current_enp_id]== 1'b1)? MCAST_PRTLw-1 : MCAST_PRTLw;
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|
|
|
end else begin
|
|
assign mcast_dst_num_o = (is_unicast)? 1 : MCAST_PRTLw;
|
|
end
|
|
/* verilator lint_on WIDTH */
|
|
end else begin : mcast
|
|
accumulator #(
|
|
.INw(NE),
|
|
.OUTw(NEw),
|
|
.NUM(NE)
|
|
)accum
|
|
(
|
|
.in_all(dest_mcast_all_endp1),
|
|
.out(sum_temp)
|
|
);
|
|
assign mcast_dst_num_o = sum_temp;
|
|
end
|
|
end
|
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endgenerate
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|
|
|
/***************************************************************
|
|
* simulation code
|
|
* ************************************************************/
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|
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|
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|
|
|
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|
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// synthesis translate_off
|
// synthesis translate_off
|
|
|
localparam NEw=log2(NE);
|
|
wire [NEw-1: 0] src_id,dst_id,current_id;
|
wire [NEw-1: 0] src_id,dst_id,current_id;
|
|
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod1 ( .id(current_id), .code(current_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod1 ( .id(current_id), .code(current_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod2 ( .id(dst_id), .code(rd_des_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod2 ( .id(dst_id), .code(rd_des_e_addr[EAw-1 : 0]));// only for unicast
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod3 ( .id(src_id), .code(rd_src_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) decod3 ( .id(src_id), .code(rd_src_e_addr));
|
|
|
|
|
|
|
|
|
|
|
|
wire [NE-1 :0] dest_mcast_all_endp2;
|
|
generate
|
|
if(CAST_TYPE != "UNICAST") begin :no_unicast
|
|
mcast_dest_list_decode decode2 (
|
|
.dest_e_addr(rd_des_e_addr),
|
|
.dest_o(dest_mcast_all_endp2),
|
|
.row_has_any_dest(),
|
|
.is_unicast()
|
|
);
|
|
end endgenerate
|
|
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(flit_out_wr && hdr_flit && dest_e_addr_reg == current_e_addr && SELF_LOOP_EN == "NO") begin
|
/* verilator lint_off WIDTH */
|
$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint (%h).: %m",$time, dest_e_addr );
|
if(CAST_TYPE == "UNICAST") begin
|
|
/* verilator lint_on WIDTH */
|
|
if(flit_out_wr && hdr_flit && dest_e_addr_o [EAw-1 : 0] == current_e_addr && SELF_LOOP_EN == "NO") begin
|
|
$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint (%h).: %m",$time, dest_e_addr_o );
|
$finish;
|
$finish;
|
end
|
end
|
if(flit_in_wr && rd_hdr_flg && (rd_des_e_addr != current_e_addr )) begin
|
if(flit_in_wr && rd_hdr_flg && (rd_des_e_addr[EAw-1 : 0] != current_e_addr )) begin
|
$display("%t: ERROR: packet with destination %d (code %h) which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h). %m",$time,dst_id,rd_des_e_addr, src_id,rd_src_e_addr, current_id,current_e_addr);
|
$display("%t: ERROR: packet with destination %d (code %h) which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h). %m",$time,dst_id,rd_des_e_addr, src_id,rd_src_e_addr, current_id,current_e_addr);
|
$finish;
|
$finish;
|
end
|
end
|
|
|
|
end else begin
|
|
/* verilator lint_off WIDTH */
|
|
if((CAST_TYPE == "MULTICAST_FULL") || (CAST_TYPE == "MULTICAST_PARTIAL")) begin
|
|
/* verilator lint_on WIDTH */
|
|
|
|
if(flit_out_wr && hdr_flit && dest_mcast_all_endp1[current_id] == 1'b1 && SELF_LOOP_EN == "NO") begin
|
|
$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint %d. destination nodes:0X%h. : %m",$time, current_id,dest_mcast_all_endp1 );
|
|
$finish;
|
|
end
|
|
end
|
|
if(flit_in_wr && rd_hdr_flg && (dest_mcast_all_endp2[current_id] !=1'b1 )) begin
|
|
$display("%t: ERROR: packet with destination %b which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h). %m",$time, dest_mcast_all_endp2, src_id,rd_src_e_addr, current_id,current_e_addr);
|
|
$finish;
|
|
end
|
|
|
|
//check multicast packet size to be smaller than B & LB
|
|
if(flit_out_wr & hdr_flit & (mcast_dst_num_o>1) & (pck_size >B || pck_size> LB))begin
|
|
$display("%t: ERROR: A multicast packat is injected to the NoC which has larger size (%d) than router buffer width. %m",$time, pck_size);
|
|
$finish;
|
|
end
|
|
|
|
end
|
if(update) begin
|
if(update) begin
|
if (hdr_flit_timestamp<= rd_timestamp) begin
|
if (hdr_flit_timestamp<= rd_timestamp) begin
|
$display("%t: ERROR: In destination %d packt which is sent by source %d, the time when header flit is recived (%d) should be larger than the packet timestamp %d. %m",$time, current_id ,src_e_addr, hdr_flit_timestamp, rd_timestamp);
|
$display("%t: ERROR: In destination %d packt which is sent by source %d, the time when header flit is recived (%d) should be larger than the packet timestamp %d. %m",$time, current_id ,src_e_addr, hdr_flit_timestamp, rd_timestamp);
|
$finish;
|
$finish;
|
end
|
end
|
| Line 678... |
Line 773... |
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
// synthesis translate_on
|
|
// synopsys translate_on
|
|
|
|
|
|
`ifdef CHECK_PCKS_CONTENT
|
`ifdef CHECK_PCKS_CONTENT
|
// synopsys translate_off
|
|
// synthesis translate_off
|
|
|
|
wire [PCK_SIZw-1 : 0] rsv_flit_counter;
|
wire [PCK_SIZw-1 : 0] rsv_flit_counter;
|
reg [PCK_SIZw-1 : 0] old_flit_counter [V-1 : 0];
|
reg [PCK_SIZw-1 : 0] old_flit_counter [V-1 : 0];
|
wire [PCK_CNTw-1 : 0] rsv_pck_number;
|
wire [PCK_CNTw-1 : 0] rsv_pck_number;
|
reg [PCK_CNTw-1 : 0] old_pck_number [V-1 : 0];
|
reg [PCK_CNTw-1 : 0] old_pck_number [V-1 : 0];
|
| Line 702... |
Line 794... |
endgenerate
|
endgenerate
|
|
|
|
|
|
|
integer ii;
|
integer ii;
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
always @ (`pronoc_clk_reset_edge )begin
|
`else
|
if(`pronoc_reset) begin
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset) begin
|
|
for(ii=0;ii
|
for(ii=0;ii
|
old_flit_counter[ii]<=0;
|
old_flit_counter[ii]<=0;
|
end
|
end
|
end else begin
|
end else begin
|
if(flit_in_wr)begin
|
if(flit_in_wr)begin
|
| Line 721... |
Line 810... |
end else if ( flit_in[Fw-1:Fw-2]==2'b00)begin
|
end else if ( flit_in[Fw-1:Fw-2]==2'b00)begin
|
old_pck_number[rd_vc_bin]<=rsv_pck_number;
|
old_pck_number[rd_vc_bin]<=rsv_pck_number;
|
old_flit_counter[rd_vc_bin]<=rsv_flit_counter;
|
old_flit_counter[rd_vc_bin]<=rsv_flit_counter;
|
end
|
end
|
|
|
end
|
end //flit_in_wr
|
|
|
end
|
end //reset
|
end
|
end//always
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(flit_in_wr && (flit_in[Fw-1:Fw-2]==2'b00) && (~reset))begin
|
if(flit_in_wr && (flit_in[Fw-1:Fw-2]==2'b00) && (~reset))begin
|
if( old_flit_counter[rd_vc_bin]!=rsv_flit_counter-1) $display("%t: Error: missmatch flit counter in %m. Expected %d but recieved %d",$time,old_flit_counter[rd_vc_bin]+1,rsv_flit_counter);
|
if( old_flit_counter[rd_vc_bin]!=rsv_flit_counter-1) $display("%t: Error: missmatch flit counter in %m. Expected %d but recieved %d",$time,old_flit_counter[rd_vc_bin]+1,rsv_flit_counter);
|
if( old_pck_number[rd_vc_bin]!=rsv_pck_number && old_pck_number[rd_vc_bin]!=0) $display("%t: Error: missmatch pck number in %m. expected %d but recieved %d",$time,old_pck_number[rd_vc_bin],rsv_pck_number);
|
if( old_pck_number[rd_vc_bin]!=rsv_pck_number && old_pck_number[rd_vc_bin]!=0) $display("%t: Error: missmatch pck number in %m. expected %d but recieved %d",$time,old_pck_number[rd_vc_bin],rsv_pck_number);
|
|
|
end
|
end
|
|
|
end
|
end
|
// synthesis translate_on
|
|
// synopsys translate_on
|
|
|
|
`endif
|
`endif
|
|
|
|
// synthesis translate_on
|
|
|
|
|
|
|
|
|
|
|
// `ifdef VERILATOR
|
// `ifdef VERILATOR
|
// logic endp_is_active /*verilator public_flat_rd*/ ;
|
// logic endp_is_active /*verilator public_flat_rd*/ ;
|
//
|
//
|
// always @ (*) begin
|
// always @ (*) begin
|
// endp_is_active = 1'b0;
|
// endp_is_active = 1'b0;
|
| Line 852... |
Line 946... |
end
|
end
|
|
|
|
|
|
|
|
|
`ifdef SYNC_RESET_MODE
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (posedge clk )begin
|
if(`pronoc_reset) begin
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if( reset) begin
|
|
state <= STATE_INIT;
|
state <= STATE_INIT;
|
inject <= 1'b0;
|
inject <= 1'b0;
|
sent <= 1'b1;
|
sent <= 1'b1;
|
flit_counter<= 0;
|
flit_counter<= 0;
|
pck_size<=2;
|
pck_size<=2;
|
| Line 891... |
Line 981... |
/*************************************
|
/*************************************
|
packet_buffer
|
packet_buffer
|
**************************************/
|
**************************************/
|
|
|
|
|
module packet_gen #(
|
module packet_gen
|
|
import pronoc_pkg::*;
|
|
#(
|
parameter P = 5,
|
parameter P = 5,
|
parameter T1= 4,
|
parameter PCK_TYPE = "SINGLE_FLIT",
|
parameter T2= 4,
|
|
parameter T3= 4,
|
|
parameter RAw = 3,
|
|
parameter EAw = 3,
|
|
parameter TOPOLOGY = "MESH",
|
|
parameter DSTPw = 4,
|
|
parameter ROUTE_NAME = "XY",
|
|
parameter ROUTE_TYPE = "DETERMINISTIC",
|
parameter ROUTE_TYPE = "DETERMINISTIC",
|
parameter MAX_PCK_NUM = 10000,
|
parameter MAX_PCK_NUM = 10000,
|
parameter MAX_SIM_CLKs = 100000,
|
parameter MAX_SIM_CLKs = 100000,
|
parameter TIMSTMP_FIFO_NUM=16,
|
parameter TIMSTMP_FIFO_NUM=16,
|
parameter MIN_PCK_SIZE=2,
|
parameter MIN_PCK_SIZE=2,
|
parameter MAX_PCK_SIZ=100
|
parameter MAX_PCK_SIZ=100
|
|
|
)(
|
)(
|
clk_counter,
|
clk_counter,
|
pck_wr,
|
pck_wr,
|
pck_rd,
|
pck_rd,
|
current_r_addr,
|
current_r_addr,
|
current_e_addr,
|
current_e_addr,
|
pck_number,
|
pck_number,
|
dest_e_addr,
|
dest_e_addr_in,
|
|
dest_e_addr_o,
|
pck_timestamp,
|
pck_timestamp,
|
destport,
|
destport,
|
buffer_full,
|
buffer_full,
|
pck_ready,
|
pck_ready,
|
valid_dst,
|
valid_dst,
|
| Line 947... |
Line 1032... |
input reset,clk, pck_wr, pck_rd;
|
input reset,clk, pck_wr, pck_rd;
|
input [RAw-1 :0] current_r_addr;
|
input [RAw-1 :0] current_r_addr;
|
input [EAw-1 : 0] current_e_addr;
|
input [EAw-1 : 0] current_e_addr;
|
input [CLK_CNTw-1 :0] clk_counter;
|
input [CLK_CNTw-1 :0] clk_counter;
|
input [PCK_SIZw-1 :0] pck_size_in;
|
input [PCK_SIZw-1 :0] pck_size_in;
|
input [EAw-1 :0] dest_e_addr;
|
input [DAw-1 :0] dest_e_addr_in;
|
|
output [DAw-1 :0] dest_e_addr_o;
|
input valid_dst;
|
input valid_dst;
|
|
|
output [PCK_CNTw-1 :0] pck_number;
|
output [PCK_CNTw-1 :0] pck_number;
|
output [CLK_CNTw-1 :0] pck_timestamp;
|
output [CLK_CNTw-1 :0] pck_timestamp;
|
output [PCK_SIZw-1 :0] pck_size_o;
|
output [PCK_SIZw-1 :0] pck_size_o;
|
| Line 961... |
Line 1047... |
reg [PCK_CNTw-1 :0] packet_counter;
|
reg [PCK_CNTw-1 :0] packet_counter;
|
wire buffer_empty;
|
wire buffer_empty;
|
|
|
assign pck_ready = ~buffer_empty & valid_dst;
|
assign pck_ready = ~buffer_empty & valid_dst;
|
|
|
|
generate if(CAST_TYPE == "UNICAST") begin : uni
|
conventional_routing #(
|
conventional_routing #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.T1(T1),
|
.T1(T1),
|
| Line 979... |
Line 1065... |
routing_module
|
routing_module
|
(
|
(
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.dest_e_addr(dest_e_addr),
|
.dest_e_addr(dest_e_addr_o),
|
.src_e_addr(current_e_addr),
|
.src_e_addr(current_e_addr),
|
.destport(destport)
|
.destport(destport)
|
);
|
);
|
|
end endgenerate
|
|
|
wire timestamp_fifo_nearly_full , timestamp_fifo_full;
|
wire timestamp_fifo_nearly_full , timestamp_fifo_full;
|
assign buffer_full = (MIN_PCK_SIZE==1) ? timestamp_fifo_nearly_full : timestamp_fifo_full;
|
assign buffer_full = (MIN_PCK_SIZE==1) ? timestamp_fifo_nearly_full : timestamp_fifo_full;
|
|
|
|
wire [DAw-1 :0] tmp1;
|
|
wire [PCK_SIZw-1 : 0] tmp2;
|
|
|
wire recieve_more_than_0;
|
wire recieve_more_than_0;
|
fwft_fifo_bram #(
|
fwft_fifo_bram #(
|
.DATA_WIDTH(CLK_CNTw+PCK_SIZw),
|
.DATA_WIDTH(CLK_CNTw+PCK_SIZw+DAw),
|
.MAX_DEPTH(TIMSTMP_FIFO_NUM)
|
.MAX_DEPTH(TIMSTMP_FIFO_NUM)
|
)
|
)
|
timestamp_fifo
|
timestamp_fifo
|
(
|
(
|
.din({pck_size_in,clk_counter}),
|
.din({dest_e_addr_in,pck_size_in,clk_counter}),
|
.wr_en(pck_wr),
|
.wr_en(pck_wr),
|
.rd_en(pck_rd),
|
.rd_en(pck_rd),
|
.dout({pck_size_o,pck_timestamp}),
|
.dout({tmp1,tmp2,pck_timestamp}),
|
.full(timestamp_fifo_full),
|
.full(timestamp_fifo_full),
|
.nearly_full(timestamp_fifo_nearly_full),
|
.nearly_full(timestamp_fifo_nearly_full),
|
.recieve_more_than_0(recieve_more_than_0),
|
.recieve_more_than_0(recieve_more_than_0),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
|
//assign dest_e_addr_o = dest_e_addr_in;
|
|
|
|
assign dest_e_addr_o =tmp1;
|
|
/* verilator lint_off WIDTH */
|
|
assign pck_size_o = (PCK_TYPE == "SINGLE_FLIT" )? 1 : tmp2;
|
|
/* verilator lint_on WIDTH */
|
assign buffer_empty = ~recieve_more_than_0;
|
assign buffer_empty = ~recieve_more_than_0;
|
|
|
/*
|
/*
|
|
|
bram_based_fifo #(
|
bram_based_fifo #(
|
| Line 1029... |
Line 1124... |
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
*/
|
*/
|
|
|
`ifdef SYNC_RESET_MODE
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (posedge clk )begin
|
if(`pronoc_reset) begin
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset) begin
|
|
packet_counter <= {PCK_CNTw{1'b0}};
|
packet_counter <= {PCK_CNTw{1'b0}};
|
|
|
end else begin
|
end else begin
|
if(pck_rd) begin
|
if(pck_rd) begin
|
packet_counter <= packet_counter+1'b1;
|
packet_counter <= packet_counter+1'b1;
|
|
|
end
|
end
|
