URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ni/] [ni_master.sv] - Diff between revs 48 and 54

Rev 48	Rev 54
Line 575...	Line 575...

`end`	`end`



	`assign chan_out.ctrl_chanel.endp_port =1'b1;`



`for (i=0;i`	`for (i=0;i`

Line 983...	Line 983...



`wire [Fw-1 : 0] fifo_dout;`	`wire [Fw-1 : 0] fifo_dout;`

	`localparam LBw = log2(LB);`

`flit_buffer #(`	`flit_buffer #(`
`.V(V),`
`.B(LB),`	`.B(LB),`
`.PCK_TYPE(PCK_TYPE),`
`.Fw(Fw),`
`.DEBUG_EN(DEBUG_EN),`
`.SSA_EN("NO")`	`.SSA_EN("NO")`
`)`	`)`
`the_ififo`	`the_ififo`
`(`	`(`
`.din(flit_in), // Data in`	`.din(flit_in), // Data in`
`.vc_num_wr(flit_in_vc_num),//write vertual chanel`	`.vc_num_wr(flit_in_vc_num),//write virtual chanel`
`.wr_en(flit_in_wr), // Write enable`	`.wr_en(flit_in_wr), // Write enable`
`.vc_num_rd(receive_vc_enable),//read vertual chanel`	`.vc_num_rd(receive_vc_enable),//read virtual chanel`
`.rd_en(fifo_rd), // Read the next word`	`.rd_en(fifo_rd), // Read the next word`
`.dout(fifo_dout), // Data out`	`.dout(fifo_dout), // Data out`
`.vc_not_empty(ififo_vc_not_empty),`	`.vc_not_empty(ififo_vc_not_empty),`
`.reset(reset),`	`.reset(reset),`
`.clk(clk),`	`.clk(clk),`
`.ssa_rd({V{1'b0}})`	`.ssa_rd({V{1'b0}}),`
	`.multiple_dest(),`
	`.sub_rd_ptr_ld()`
`);`	`);`

`extract_header_flit_info #(`	`extract_header_flit_info #(`
`.DATA_w (HDw)`	`.DATA_w (HDw)`
`)`	`)`