URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [arbiter.v] - Diff between revs 38 and 48

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Rev 38	Rev 48
Line 206...	Line 206...
`.bin_code(grant_bcd)`	`.bin_code(grant_bcd)`

`);`	`);`


	`ifdef SYNC_RESET_MODE
	`always @ (posedge clk )begin`
	`else
`always@(posedge clk or posedge reset) begin`	`always@(posedge clk or posedge reset) begin`
	`endif

`if(reset) begin`	`if(reset) begin`
`low_pr <= {ARBITER_BIN_WIDTH{1'b0}};`	`low_pr <= {ARBITER_BIN_WIDTH{1'b0}};`
`end else begin`	`end else begin`
`if(any_grant) low_pr <= grant_bcd;`	`if(any_grant) low_pr <= grant_bcd;`
`end`	`end`
Line 351...	Line 355...
`(`	`(`
`.one_hot_code(grant),`	`.one_hot_code(grant),`
`.bin_code(grant_bcd)`	`.bin_code(grant_bcd)`
`);`	`);`

	`ifdef SYNC_RESET_MODE
	`always @ (posedge clk )begin`
	`else
`always@(posedge clk or posedge reset) begin`	`always@(posedge clk or posedge reset) begin`
	`endif

`if(reset) begin`	`if(reset) begin`
`low_pr <= {ARBITER_BIN_WIDTH{1'b0}};`	`low_pr <= {ARBITER_BIN_WIDTH{1'b0}};`
`end else begin`	`end else begin`
`if(priority_en) low_pr <= grant_bcd;`	`if(priority_en) low_pr <= grant_bcd;`
`end`	`end`
Line 447...	Line 456...

`assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;`	`assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;`
`assign masked_request= request & pr;`	`assign masked_request= request & pr;`
`assign any_grant=termo1[ARBITER_WIDTH-1];`	`assign any_grant=termo1[ARBITER_WIDTH-1];`

	`ifdef SYNC_RESET_MODE
	`always @ (posedge clk )begin`
	`else
`always @(posedge clk or posedge reset)begin`	`always @(posedge clk or posedge reset)begin`
	`endif
`if(reset) pr<= {ARBITER_WIDTH{1'b1}};`	`if(reset) pr<= {ARBITER_WIDTH{1'b1}};`
`else begin`	`else begin`
`if(any_grant) pr<= edge_mask;`	`if(any_grant) pr<= edge_mask;`
`end`	`end`

`end`	`end`

`assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};`	`assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};`
`assign grant= mux_out ^ edge_mask;`	`assign grant= mux_out ^ edge_mask;`

Line 516...	Line 528...

`assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;`	`assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;`
`assign masked_request= request & pr;`	`assign masked_request= request & pr;`
`assign any_grant=termo1[ARBITER_WIDTH-1];`	`assign any_grant=termo1[ARBITER_WIDTH-1];`

	`ifdef SYNC_RESET_MODE
	`always @ (posedge clk )begin`
	`else
`always @(posedge clk or posedge reset)begin`	`always @(posedge clk or posedge reset)begin`
	`endif


`if(reset) pr<= {ARBITER_WIDTH{1'b1}};`	`if(reset) pr<= {ARBITER_WIDTH{1'b1}};`
`else begin`	`else begin`
`if(priority_en) pr<= edge_mask;`	`if(priority_en) pr<= edge_mask;`
`end`	`end`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [arbiter.v] - Diff between revs 38 and 48