URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [jtag_wb/] [vjtag_wb.v] - Diff between revs 38 and 48

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Rev 38	Rev 48
Line 91...	Line 91...
`.wb_rd_data_en(wb_rd_data_en),`	`.wb_rd_data_en(wb_rd_data_en),`
`.status_i(status_i)`	`.status_i(status_i)`
`);`	`);`


	`ifdef SYNC_RESET_MODE
	`always @ (posedge clk )begin`
	`else
`always @(posedge clk or posedge reset) begin`	`always @(posedge clk or posedge reset) begin`
	`endif

`if(reset) begin`	`if(reset) begin`
`wb_addr <= {AW{1'b0}};`	`wb_addr <= {AW{1'b0}};`
`wb_wr_data <= {DW{1'b0}};`	`wb_wr_data <= {DW{1'b0}};`
`ps <= IDEAL;`	`ps <= IDEAL;`
`end else begin`	`end else begin`
Line 230...	Line 234...
`assign ir_out = ir_in; // Just pass the IR out`	`assign ir_out = ir_in; // Just pass the IR out`
`assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];`	`assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];`
`assign data_out = shift_buffer;`	`assign data_out = shift_buffer;`


	`ifdef SYNC_RESET_MODE
	`always @ (posedge tck )begin`
	`else
	`always @ (posedge tck or posedge reset)begin`
	`endif


`always @(posedge tck or posedge reset)`
`begin`
`if (reset)begin`	`if (reset)begin`
`ir <= 3'b000;`	`ir <= 3'b000;`
`bypass_reg<=1'b0;`	`bypass_reg<=1'b0;`
`shift_buffer<={DW{1'b0}};`	`shift_buffer<={DW{1'b0}};`

Line 282...	Line 288...
`end`	`end`

`reg wb_wr_addr2, wb_wr_data2, wb_rd_data2;`	`reg wb_wr_addr2, wb_wr_data2, wb_rd_data2;`
`reg wb_wr_addr3, wb_wr_data3, wb_rd_data3;`	`reg wb_wr_addr3, wb_wr_data3, wb_rd_data3;`

`always @(posedge clk or posedge reset)`	`ifdef SYNC_RESET_MODE
`begin`	`always @ (posedge clk )begin`
	`else
	`always @ (posedge clk or posedge reset)begin`
	`endif

`if( reset ) begin`	`if( reset ) begin`
`wb_wr_addr2<=1'b0;`	`wb_wr_addr2<=1'b0;`
`wb_wr_data2<=1'b0;`	`wb_wr_data2<=1'b0;`
`wb_wr_addr3<=1'b0;`	`wb_wr_addr3<=1'b0;`
`wb_wr_data3<=1'b0;`	`wb_wr_data3<=1'b0;`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [jtag_wb/] [vjtag_wb.v] - Diff between revs 38 and 48