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Line 34... |
module wb_single_port_ram #(
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module wb_single_port_ram #(
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parameter Dw=32, //RAM data_width in bits
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parameter Dw=32, //RAM data_width in bits
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parameter Aw=10, //RAM address width
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parameter Aw=10, //RAM address width
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_INDEX= 0,
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parameter JTAG_INDEX= 0,
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parameter INITIAL_EN= "NO",
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parameter INITIAL_EN= "NO",
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parameter MEM_CONTENT_FILE_NAME= "ram0",// ram initial file name
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parameter MEM_CONTENT_FILE_NAME= "ram0",// ram initial file name
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parameter INIT_FILE_PATH = "path_to/sw", // The sw folder path. It will be used for finding initial file. The path will be rewriten by the top module.
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parameter INIT_FILE_PATH = "path_to/sw", // The sw folder path. It will be used for finding initial file. The path will be rewriten by the top module.
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// wishbon bus param
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// wishbon bus param
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Line 190... |
module single_port_ram_top #(
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module single_port_ram_top #(
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parameter Dw=32, //RAM data_width in bits
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parameter Dw=32, //RAM data_width in bits
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parameter Aw=10, //RAM address width
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parameter Aw=10, //RAM address width
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_INDEX= 0,
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parameter JTAG_INDEX= 0,
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parameter INITIAL_EN= "NO",
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parameter INITIAL_EN= "NO",
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parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file
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parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file
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)
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)
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addr_a,
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addr_a,
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byteena_a,
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byteena_a,
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we_a,
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we_a,
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q_a
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q_a
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);
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);
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/* verilator lint_off WIDTH */
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localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
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localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
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/* verilator lint_on WIDTH */
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input clk,reset;
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input clk,reset;
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input [Dw-1 : 0] data_a;
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input [Dw-1 : 0] data_a;
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input [Aw-1 : 0] addr_a;
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input [Aw-1 : 0] addr_a;
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input we_a;
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input we_a;
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Line 252... |
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generate
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generate
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/* verilator lint_off WIDTH */
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if(FPGA_VENDOR=="ALTERA")begin:altera_fpga
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if(FPGA_VENDOR=="ALTERA")begin:altera_fpga
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/* verilator lint_on WIDTH */
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localparam RAM_TAG_STRING=i2s(JTAG_INDEX);
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localparam RAM_TAG_STRING=i2s(JTAG_INDEX);
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localparam RAM_ID =(JTAG_CONNECT== "ALTERA_IMCE") ? {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}
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localparam RAM_ID =(JTAG_CONNECT== "ALTERA_IMCE") ? {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}
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: {"ENABLE_RUNTIME_MOD=NO"};
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: {"ENABLE_RUNTIME_MOD=NO"};
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/* verilator lint_off WIDTH */
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if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram
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if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram
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/* verilator lint_on WIDTH */
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// aletra dual port ram
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// aletra dual port ram
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altsyncram #(
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altsyncram #(
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.operation_mode("BIDIR_DUAL_PORT"),
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.operation_mode("BIDIR_DUAL_PORT"),
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.address_reg_b("CLOCK0"),
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.address_reg_b("CLOCK0"),
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.wrcontrol_wraddress_reg_b("CLOCK0"),
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.wrcontrol_wraddress_reg_b("CLOCK0"),
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Line 354... |
.eccstatus ( )
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.eccstatus ( )
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);
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);
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end
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end
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end
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end
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/* verilator lint_off WIDTH */
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else if(FPGA_VENDOR=="GENERIC")begin:generic_ram
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else if(FPGA_VENDOR=="GENERIC")begin:generic_ram
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if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram
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if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram
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/* verilator lint_on WIDTH */
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generic_dual_port_ram #(
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generic_dual_port_ram #(
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.Dw(Dw),
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.Dw(Dw),
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.Aw(Aw),
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.Aw(Aw),
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.BYTE_WR_EN(BYTE_WR_EN),
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.BYTE_WR_EN(BYTE_WR_EN),
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| Line 403... |
Line 408... |
);
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);
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end//jtag_wb
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end//jtag_wb
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end //Generic
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end //Generic
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/* verilator lint_off WIDTH */
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if(JTAG_CONNECT == "JTAG_WB")begin:jtag_wb
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if(JTAG_CONNECT == "ALTERA_JTAG_WB")begin:jtag_wb
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/* verilator lint_on WIDTH */
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reg jtag_ack;
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reg jtag_ack;
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wire jtag_we_o, jtag_stb_o;
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wire jtag_we_o, jtag_stb_o;
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localparam Sw= log2(Aw+1);
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localparam Sw= log2(Aw+1);
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localparam [Sw-1 : 0] ST = Aw;
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localparam [Sw-1 : 0] ST = Aw;
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