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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [ram_test.v] - Diff between revs 38 and 48

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Rev 38 Rev 48
Line 55... Line 55... 
              end
 
              end
 
              i2s = tmp[15:0];
 
              i2s = tmp[15:0];
 
          end
 
          end
 
     endfunction //i2s
 
     endfunction //i2s
 
 
 
 
 
        localparam      programer_DW=32;
 
        localparam      programmer_DW=32;
 
        localparam      programer_AW=32;
 
        localparam      programmer_AW=32;
 
        localparam      programer_S_Aw=   7;
 
        localparam      programmer_S_Aw=   7;
 
        localparam      programer_M_Aw=   32;
 
        localparam      programmer_M_Aw=   32;
 
        localparam      programer_TAGw=   3;
 
        localparam      programmer_TAGw=   3;
 
        localparam      programer_SELw=   4;
 
        localparam      programmer_SELw=   4;
 
        localparam      programer_VJTAG_INDEX=CORE_ID;
 
        localparam      programmer_VJTAG_INDEX=CORE_ID;
 
 
 
 
 
        localparam      ram_BYTE_WR_EN="YES";
 
        localparam      ram_BYTE_WR_EN="YES";
 
        localparam      ram_FPGA_VENDOR="ALTERA";
 
        localparam      ram_FPGA_VENDOR="ALTERA";
 
        localparam      ram_JTAG_CONNECT= "ALTERA_IMCE";
 
        localparam      ram_JTAG_CONNECT= "ALTERA_IMCE";
 
        localparam      ram_JTAG_INDEX=CORE_ID;
 
        localparam      ram_JTAG_INDEX=CORE_ID;
Line 101... Line 101... 
        input                   ss_reset_in;
 
        input                   ss_reset_in;
 
 
 
 
 
        wire                     ss_socket_clk_0_clk_o;
 
        wire                     ss_socket_clk_0_clk_o;
 
        wire                     ss_socket_reset_0_reset_o;
 
        wire                     ss_socket_reset_0_reset_o;
 
 
 
 
 
        wire                     programer_plug_clk_0_clk_i;
 
        wire                     programmer_plug_clk_0_clk_i;
 
        wire                     programer_plug_wb_master_0_ack_i;
 
        wire                     programmer_plug_wb_master_0_ack_i;
 
        wire    [ programer_M_Aw-1          :   0 ] programer_plug_wb_master_0_adr_o;
 
        wire    [ programmer_M_Aw-1          :   0 ] programmer_plug_wb_master_0_adr_o;
 
        wire    [ programer_TAGw-1          :   0 ] programer_plug_wb_master_0_cti_o;
 
        wire    [ programmer_TAGw-1          :   0 ] programmer_plug_wb_master_0_cti_o;
 
        wire                     programer_plug_wb_master_0_cyc_o;
 
        wire                     programmer_plug_wb_master_0_cyc_o;
 
        wire    [ programer_DW-1           :  0 ] programer_plug_wb_master_0_dat_i;
 
        wire    [ programmer_DW-1           :  0 ] programmer_plug_wb_master_0_dat_i;
 
        wire    [ programer_DW-1            :   0 ] programer_plug_wb_master_0_dat_o;
 
        wire    [ programmer_DW-1            :   0 ] programmer_plug_wb_master_0_dat_o;
 
        wire    [ programer_SELw-1          :   0 ] programer_plug_wb_master_0_sel_o;
 
        wire    [ programmer_SELw-1          :   0 ] programmer_plug_wb_master_0_sel_o;
 
        wire                     programer_plug_wb_master_0_stb_o;
 
        wire                     programmer_plug_wb_master_0_stb_o;
 
        wire                     programer_plug_wb_master_0_we_o;
 
        wire                     programmer_plug_wb_master_0_we_o;
 
        wire                     programer_plug_reset_0_reset_i;
 
        wire                     programmer_plug_reset_0_reset_i;
 
 
 
 
 
        wire                     ram_plug_clk_0_clk_i;
 
        wire                     ram_plug_clk_0_clk_i;
 
        wire                     ram_plug_reset_0_reset_i;
 
        wire                     ram_plug_reset_0_reset_i;
 
        wire                     ram_plug_wb_slave_0_ack_o;
 
        wire                     ram_plug_wb_slave_0_ack_o;
 
        wire    [ ram_Aw-1       :   0 ] ram_plug_wb_slave_0_adr_i;
 
        wire    [ ram_Aw-1       :   0 ] ram_plug_wb_slave_0_adr_i;
Line 199... Line 199... 
                .clk_out(ss_socket_clk_0_clk_o),
 
                .clk_out(ss_socket_clk_0_clk_o),
 
                .reset_in(ss_reset_in),
 
                .reset_in(ss_reset_in),
 
                .reset_out(ss_socket_reset_0_reset_o)
 
                .reset_out(ss_socket_reset_0_reset_o)
 
        );
 
        );
 
 vjtag_wb #(
 
 vjtag_wb #(
 
                .DW(programer_DW),
 
                .DW(programmer_DW),
 
                .AW(programer_AW),
 
                .AW(programmer_AW),
 
                .S_Aw(programer_S_Aw),
 
                .S_Aw(programmer_S_Aw),
 
                .M_Aw(programer_M_Aw),
 
                .M_Aw(programmer_M_Aw),
 
                .TAGw(programer_TAGw),
 
                .TAGw(programmer_TAGw),
 
                .SELw(programer_SELw),
 
                .SELw(programmer_SELw),
 
                .VJTAG_INDEX(programer_VJTAG_INDEX)
 
                .VJTAG_INDEX(programmer_VJTAG_INDEX)
 
        )  programer    (
 
        )  programmer   (
 
                .clk(programer_plug_clk_0_clk_i),
 
                .clk(programmer_plug_clk_0_clk_i),
 
                .m_ack_i(programer_plug_wb_master_0_ack_i),
 
                .m_ack_i(programmer_plug_wb_master_0_ack_i),
 
                .m_addr_o(programer_plug_wb_master_0_adr_o),
 
                .m_addr_o(programmer_plug_wb_master_0_adr_o),
 
                .m_cti_o(programer_plug_wb_master_0_cti_o),
 
                .m_cti_o(programmer_plug_wb_master_0_cti_o),
 
                .m_cyc_o(programer_plug_wb_master_0_cyc_o),
 
                .m_cyc_o(programmer_plug_wb_master_0_cyc_o),
 
                .m_dat_i(programer_plug_wb_master_0_dat_i),
 
                .m_dat_i(programmer_plug_wb_master_0_dat_i),
 
                .m_dat_o(programer_plug_wb_master_0_dat_o),
 
                .m_dat_o(programmer_plug_wb_master_0_dat_o),
 
                .m_sel_o(programer_plug_wb_master_0_sel_o),
 
                .m_sel_o(programmer_plug_wb_master_0_sel_o),
 
                .m_stb_o(programer_plug_wb_master_0_stb_o),
 
                .m_stb_o(programmer_plug_wb_master_0_stb_o),
 
                .m_we_o(programer_plug_wb_master_0_we_o),
 
                .m_we_o(programmer_plug_wb_master_0_we_o),
 
                .reset(programer_plug_reset_0_reset_i),
 
                .reset(programmer_plug_reset_0_reset_i),
 
                .status_i()
 
                .status_i()
 
        );
 
        );
 
 wb_single_port_ram #(
 
 wb_single_port_ram #(
 
                .Dw(ram_Dw),
 
                .Dw(ram_Dw),
 
                .Aw(ram_Aw),
 
                .Aw(ram_Aw),
Line 250... Line 250... 
                .sa_err_o(ram_plug_wb_slave_0_err_o),
 
                .sa_err_o(ram_plug_wb_slave_0_err_o),
 
                .sa_rty_o(ram_plug_wb_slave_0_rty_o),
 
                .sa_rty_o(ram_plug_wb_slave_0_rty_o),
 
                .sa_sel_i(ram_plug_wb_slave_0_sel_i),
 
                .sa_sel_i(ram_plug_wb_slave_0_sel_i),
 
                .sa_stb_i(ram_plug_wb_slave_0_stb_i),
 
                .sa_stb_i(ram_plug_wb_slave_0_stb_i),
 
                .sa_tag_i(ram_plug_wb_slave_0_tag_i),
 
                .sa_tag_i(ram_plug_wb_slave_0_tag_i),
 
                .sa_we_i(ram_plug_wb_slave_0_we_i)
 
                .sa_we_i(ram_plug_wb_slave_0_we_i),
 
 
 
                .jtag_to_wb ( ),
 
 
 
        .wb_to_jtag ( )
 
 
 
 
 
        );
 
        );
 
 
 
 
 
 
 
 
 
 wishbone_bus #(
 
 wishbone_bus #(
 
                .M(bus_M),
 
                .M(bus_M),
 
                .S(bus_S),
 
                .S(bus_S),
 
                .Dw(bus_Dw),
 
                .Dw(bus_Dw),
 
                .Aw(bus_Aw),
 
                .Aw(bus_Aw),
Line 291... Line 296... 
                .s_rty_i_all(bus_socket_wb_slave_array_rty_i),
 
                .s_rty_i_all(bus_socket_wb_slave_array_rty_i),
 
                .s_sel_o_all(bus_socket_wb_slave_array_sel_o),
 
                .s_sel_o_all(bus_socket_wb_slave_array_sel_o),
 
                .s_sel_one_hot(bus_socket_wb_addr_map_0_sel_one_hot),
 
                .s_sel_one_hot(bus_socket_wb_addr_map_0_sel_one_hot),
 
                .s_stb_o_all(bus_socket_wb_slave_array_stb_o),
 
                .s_stb_o_all(bus_socket_wb_slave_array_stb_o),
 
                .s_tag_o_all(bus_socket_wb_slave_array_tag_o),
 
                .s_tag_o_all(bus_socket_wb_slave_array_tag_o),
 
                .s_we_o_all(bus_socket_wb_slave_array_we_o)
 
                .s_we_o_all(bus_socket_wb_slave_array_we_o),
 
 
 
                .snoop_adr_o(),
 
 
 
        .snoop_en_o()
 
        );
 
        );
 
 
 
 
 
 
 
 
 
 
 
 
 
        assign  programer_plug_clk_0_clk_i = ss_socket_clk_0_clk_o;
 
        assign  programmer_plug_clk_0_clk_i = ss_socket_clk_0_clk_o;
 
        assign  programer_plug_wb_master_0_ack_i = bus_socket_wb_master_0_ack_o;
 
        assign  programmer_plug_wb_master_0_ack_i = bus_socket_wb_master_0_ack_o;
 
        assign  bus_socket_wb_master_0_adr_i  = programer_plug_wb_master_0_adr_o;
 
        assign  bus_socket_wb_master_0_adr_i  = programmer_plug_wb_master_0_adr_o;
 
        assign  bus_socket_wb_master_0_cti_i  = programer_plug_wb_master_0_cti_o;
 
        assign  bus_socket_wb_master_0_cti_i  = programmer_plug_wb_master_0_cti_o;
 
        assign  bus_socket_wb_master_0_cyc_i  = programer_plug_wb_master_0_cyc_o;
 
        assign  bus_socket_wb_master_0_cyc_i  = programmer_plug_wb_master_0_cyc_o;
 
        assign  programer_plug_wb_master_0_dat_i = bus_socket_wb_master_0_dat_o[programer_DW-1           :  0];
 
        assign  programmer_plug_wb_master_0_dat_i = bus_socket_wb_master_0_dat_o[programmer_DW-1           :  0];
 
        assign  bus_socket_wb_master_0_dat_i  = programer_plug_wb_master_0_dat_o;
 
        assign  bus_socket_wb_master_0_dat_i  = programmer_plug_wb_master_0_dat_o;
 
        assign  bus_socket_wb_master_0_sel_i  = programer_plug_wb_master_0_sel_o;
 
        assign  bus_socket_wb_master_0_sel_i  = programmer_plug_wb_master_0_sel_o;
 
        assign  bus_socket_wb_master_0_stb_i  = programer_plug_wb_master_0_stb_o;
 
        assign  bus_socket_wb_master_0_stb_i  = programmer_plug_wb_master_0_stb_o;
 
        assign  bus_socket_wb_master_0_we_i  = programer_plug_wb_master_0_we_o;
 
        assign  bus_socket_wb_master_0_we_i  = programmer_plug_wb_master_0_we_o;
 
        assign  programer_plug_reset_0_reset_i = ss_socket_reset_0_reset_o;
 
        assign  programmer_plug_reset_0_reset_i = ss_socket_reset_0_reset_o;
 
 
 
 
 
 
 
 
 
        assign  ram_plug_clk_0_clk_i = ss_socket_clk_0_clk_o;
 
        assign  ram_plug_clk_0_clk_i = ss_socket_clk_0_clk_o;
 
        assign  ram_plug_reset_0_reset_i = ss_socket_reset_0_reset_o;
 
        assign  ram_plug_reset_0_reset_i = ss_socket_reset_0_reset_o;
 
        assign  bus_socket_wb_slave_0_ack_i  = ram_plug_wb_slave_0_ack_o;
 
        assign  bus_socket_wb_slave_0_ack_i  = ram_plug_wb_slave_0_ack_o;

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