URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [sw/] [README] - Diff between revs 38 and 48

Rev 38	Rev 48
Line 33...	Line 33...
`** Program the memories`	`** Program the memories`
`***********************`	`***********************`

`If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using`	`If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using`

`sh program.sh`	`bash program.sh`



`***************************`	`***************************`
`** soc parameters`	`** soc parameters`