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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [sw/] [aemb/] [msr.hh] - Diff between revs 17 and 48

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Rev 17 Rev 48
Line 55... Line 55...
  /**
  /**
     Read the value of the MSR register
     Read the value of the MSR register
     @return register contents
     @return register contents
  */
  */
 
 
  inline int aembGetMSR()
 static inline int aembGetMSR()
  {
  {
    int rmsr;
    int rmsr;
    asm volatile ("mfs %0, rmsr":"=r"(rmsr));
    asm volatile ("mfs %0, rmsr":"=r"(rmsr));
    return rmsr;
    return rmsr;
  }
  }
Line 67... Line 67...
  /**
  /**
     Write a value to the MSR register
     Write a value to the MSR register
     @param rmsr value to write
     @param rmsr value to write
  */
  */
 
 
  inline void aembPutMSR(int rmsr)
 static inline void aembPutMSR(int rmsr)
  {
  {
    asm volatile ("mts rmsr, %0"::"r"(rmsr));
    asm volatile ("mts rmsr, %0"::"r"(rmsr));
  }
  }
 
 
  /**
  /**
     Read and clear the MSR
     Read and clear the MSR
     @param rmsk clear mask
     @param rmsk clear mask
     @return msr value
     @return msr value
   */
   */
 
 
  inline int aembClrMSR(const short rmsk)
 static inline int aembClrMSR(const short rmsk)
  {
  {
    int tmp;
    int tmp;
    //asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory");
    //asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory");
    return tmp;
    return tmp;
  }
  }
Line 91... Line 91...
     Read and set the MSR
     Read and set the MSR
     @param rmsk set mask
     @param rmsk set mask
     @return msr value
     @return msr value
   */
   */
 
 
  inline int aembSetMSR(const short rmsk)
 static inline int aembSetMSR(const short rmsk)
  {
  {
    int tmp;
    int tmp;
    //asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory");
    //asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory");
    return tmp;
    return tmp;
  }
  }
 
 
  /** Enable global interrupts */
  /** Enable global interrupts */
  inline int aembEnableInterrupts()
 static inline int aembEnableInterrupts()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
    return msr;
    return msr;
  }
  }
 
 
  /** Disable global interrupts */
  /** Disable global interrupts */
  inline int aembDisableInterrupts()
 static inline int aembDisableInterrupts()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
    return msr;
    return msr;
  }
  }
 
 
  /** Enable global exception */
  /** Enable global exception */
  inline int aembEnableException()
 static inline int aembEnableException()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
    return msr;
    return msr;
  }
  }
 
 
  /** Disable global exception */
  /** Disable global exception */
  inline int aembDisableException()
  static inline int aembDisableException()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
    return msr;
    return msr;
  }
  }
 
 
  /** Enable data caches */
  /** Enable data caches */
  inline int aembEnableDataTag()
 static inline int aembEnableDataTag()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
    return msr;
    return msr;
  }
  }
 
 
  /** Disable data caches */
  /** Disable data caches */
  inline int aembDisableDataTag()
 static  inline int aembDisableDataTag()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
    return msr;
    return msr;
  }
  }
 
 
  /** Enable inst caches */
  /** Enable inst caches */
  inline int aembEnableInstTag()
  static inline int aembEnableInstTag()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
    asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
    return msr;
    return msr;
  }
  }
 
 
  /** Disable inst caches */
  /** Disable inst caches */
  inline int aembDisableInstTag()
 static inline int aembDisableInstTag()
  {
  {
    int msr;
    int msr;
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
    asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
    return msr;
    return msr;
  }
  }

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