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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [aemb.v] - Diff between revs 16 and 17

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Rev 16 Rev 17
Line 5... Line 5... 
  dwb_dat_o,
 
  dwb_dat_o,
 
  dwb_sel_o,
 
  dwb_sel_o,
 
  dwb_stb_o,
 
  dwb_stb_o,
 
  dwb_tag_o,
 
  dwb_tag_o,
 
  dwb_wre_o,
 
  dwb_wre_o,
 
 
 
  dwb_cti_o,
 
 
 
  dwb_bte_o,
 
  dwb_ack_i,
 
  dwb_ack_i,
 
  dwb_dat_i,
 
  dwb_dat_i,
 
 
 
 
 
  dwb_err_i,
 
  dwb_err_i,
 
  dwb_rty_i,
 
  dwb_rty_i,
 
 
 
 
 
  iwb_adr_o,
 
  iwb_adr_o,
 
  iwb_cyc_o,
 
  iwb_cyc_o,
 
  iwb_sel_o,
 
  iwb_sel_o,
 
  iwb_stb_o,
 
  iwb_stb_o,
 
  iwb_tag_o,
 
  iwb_tag_o,
 
  iwb_wre_o,
 
  iwb_wre_o,
 
 
 
  iwb_dat_o,
 
 
 
  iwb_cti_o,
 
 
 
  iwb_bte_o,
 
  iwb_ack_i,
 
  iwb_ack_i,
 
  iwb_dat_i,
 
  iwb_dat_i,
 
  iwb_dat_o,
 
 
 
 
 
 
 
  iwb_err_i,
 
  iwb_err_i,
 
  iwb_rty_i,
 
  iwb_rty_i,
 
 
 
 
 
  clk,
 
  clk,
Line 52... Line 56... 
   output [31:0] dwb_dat_o;
 
   output [31:0] dwb_dat_o;
 
   output [3:0]  dwb_sel_o;
 
   output [3:0]  dwb_sel_o;
 
   output        dwb_stb_o;
 
   output        dwb_stb_o;
 
   output  [2:0] dwb_tag_o;
 
   output  [2:0] dwb_tag_o;
 
   output        dwb_wre_o;
 
   output        dwb_wre_o;
 
 
 
   output  [2:0] dwb_cti_o;
 
 
 
   output  [1:0] dwb_bte_o;
 
 
 
 
 
 
 
 
 
   input         dwb_ack_i;
 
   input         dwb_ack_i;
 
   input [31:0]  dwb_dat_i;
 
   input [31:0]  dwb_dat_i;
 
 
 
 
 
 
 
 
 
 
 
 
Line 67... Line 75... 
   output [2:0]  iwb_tag_o;
 
   output [2:0]  iwb_tag_o;
 
   output        iwb_wre_o;
 
   output        iwb_wre_o;
 
   input         iwb_ack_i;
 
   input         iwb_ack_i;
 
   input [31:0]  iwb_dat_i;
 
   input [31:0]  iwb_dat_i;
 
   output[31:0]  iwb_dat_o;
 
   output[31:0]  iwb_dat_o;
 
 
 
   output  [2:0] iwb_cti_o;
 
 
 
   output  [1:0] iwb_bte_o;
 
 
 
 
 
   input         clk;
 
   input         clk;
 
   input        sys_ena_i;
 
   input        sys_ena_i;
 
   input        sys_int_i;
 
   input        sys_int_i;
 
   input        reset;
 
   input        reset;
 
 
 
 
 
 
 
   wire         i_tag,d_tag;
 
 
 
 
 
 // not used but added to prevent warning
 
 // not used but added to prevent warning
 
  input dwb_err_i, dwb_rty_i,  iwb_err_i, iwb_rty_i;
 
  input dwb_err_i, dwb_rty_i,  iwb_err_i, iwb_rty_i;
 
 
 
 
 
 
 
 
 
aeMB2_edk63 #(
 
aeMB2_edk63 #(
Line 97... Line 110... 
            .xwb_sel_o() ,  //   [3:0] xwb_sel_o
 
            .xwb_sel_o() ,  //   [3:0] xwb_sel_o
 
            .xwb_dat_o() ,  //   [31:0] xwb_dat_o
 
            .xwb_dat_o() ,  //   [31:0] xwb_dat_o
 
            .xwb_cyc_o() ,  //    xwb_cyc_o
 
            .xwb_cyc_o() ,  //    xwb_cyc_o
 
            .xwb_adr_o() ,  //   [AEMB_XWB-1:2] xwb_adr_o
 
            .xwb_adr_o() ,  //   [AEMB_XWB-1:2] xwb_adr_o
 
            .iwb_wre_o(iwb_wre_o) ,  //    iwb_wre_o
 
            .iwb_wre_o(iwb_wre_o) ,  //    iwb_wre_o
 
            .iwb_tag_o() ,  //    iwb_tag_o
 
            .iwb_tag_o(i_tag) ,  //    iwb_tag_o
 
            .iwb_stb_o(iwb_stb_o) ,  //    iwb_stb_o
 
            .iwb_stb_o(iwb_stb_o) ,  //    iwb_stb_o
 
            .iwb_sel_o(iwb_sel_o) ,  //   [3:0] iwb_sel_o
 
            .iwb_sel_o(iwb_sel_o) ,  //   [3:0] iwb_sel_o
 
            .iwb_cyc_o(iwb_cyc_o) ,  //    iwb_cyc_o
 
            .iwb_cyc_o(iwb_cyc_o) ,  //    iwb_cyc_o
 
            .iwb_adr_o(iwb_adr_o[29:0]) ,    //   [AEMB_IWB-1:2] iwb_adr_o
 
            .iwb_adr_o(iwb_adr_o[29:0]) ,    //   [AEMB_IWB-1:2] iwb_adr_o
 
 
 
 
 
            .dwb_wre_o(dwb_wre_o) ,  //    dwb_wre_o
 
            .dwb_wre_o(dwb_wre_o) ,  //    dwb_wre_o
 
            .dwb_tag_o() ,  //    dwb_tag_o
 
            .dwb_tag_o(d_tag) ,  //    dwb_tag_o
 
            .dwb_stb_o(dwb_stb_o) ,  //    dwb_stb_o
 
            .dwb_stb_o(dwb_stb_o) ,  //    dwb_stb_o
 
            .dwb_sel_o(dwb_sel_o) ,  //   [3:0] dwb_sel_o
 
            .dwb_sel_o(dwb_sel_o) ,  //   [3:0] dwb_sel_o
 
            .dwb_dat_o(dwb_dat_o) ,  //   [31:0] dwb_dat_o
 
            .dwb_dat_o(dwb_dat_o) ,  //   [31:0] dwb_dat_o
 
            .dwb_cyc_o(dwb_cyc_o) ,  //    dwb_cyc_o
 
            .dwb_cyc_o(dwb_cyc_o) ,  //    dwb_cyc_o
 
            .dwb_adr_o(dwb_adr_o [29:0]) ,    //   [AEMB_DWB-1:2] dwb_adr_o
 
            .dwb_adr_o(dwb_adr_o [29:0]) ,    //   [AEMB_DWB-1:2] dwb_adr_o
Line 125... Line 138... 
            .dwb_dat_i(dwb_dat_i) ,  // input [31:0] dwb_dat_i
 
            .dwb_dat_i(dwb_dat_i) ,  // input [31:0] dwb_dat_i
 
            .dwb_ack_i(dwb_ack_i)    // input  dwb_ack_i
 
            .dwb_ack_i(dwb_ack_i)    // input  dwb_ack_i
 
        );
 
        );
 
 
 
 
 
        assign iwb_dat_o = 0;
 
        assign iwb_dat_o = 0;
 
        assign iwb_tag_o = 3'b000;  // clasic wishbone without  burst 
        // I have no idea which tag (a,b or c) is used in aemb. I assume it is address tag (taga) 
        assign dwb_tag_o = 3'b000;  // clasic wishbone without  burst 
        assign iwb_tag_o        = {i_tag,2'b00};
 
 
 
        assign dwb_tag_o        = {d_tag,2'b00};
 
        assign iwb_adr_o[31:30]  =   2'b00;
 
        assign iwb_adr_o[31:30]  =   2'b00;
 
        assign dwb_adr_o[31:30]  =   2'b00;
 
        assign dwb_adr_o[31:30]  =   2'b00;
 
 
 
        assign dwb_cti_o        = 3'd0;
 
 
 
        assign dwb_bte_o        = 2'd0;
 
 
 
        assign iwb_cti_o        = 3'd0;
 
 
 
        assign iwb_bte_o        = 2'd0;
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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