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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [aemb.v] - Diff between revs 17 and 34

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Rev 17 Rev 34
Line 1... Line 1...
 
 `timescale  1ns/1ps
 
 
module aeMB_top (
module aeMB_top (
 
 
  dwb_adr_o,
  dwb_adr_o,
  dwb_cyc_o,
  dwb_cyc_o,
  dwb_dat_o,
  dwb_dat_o,

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