URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_sim.v] - Diff between revs 16 and 48

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Rev 16	Rev 48
Line 120...	Line 120...
`wire [31:0] wMSR = sim.aslu.wMSR[31:0];`	`wire [31:0] wMSR = sim.aslu.wMSR[31:0];`

`always @(posedge sim.clk_i) if (sim.ena_i) begin`	`always @(posedge sim.clk_i) if (sim.ena_i) begin`

`$write ("\n", ($stime/10));`	`$write ("\n", ($stime/10));`
`$writeh (" T", sim.pha_i);`	`$write (" T", sim.pha_i);`
`$writeh(" PC=", iwb_adr);`	`$write(" PC=", iwb_adr);`

`$writeh ("\t\| ");`	`$write ("\t\| ");`

`case (sim.rOPC_IF)`	`case (sim.rOPC_IF)`
`6'o00: if (sim.rRD_IF == 0) $write(" "); else $write("ADD");`	`6'o00: if (sim.rRD_IF == 0) $write(" "); else $write("ADD");`
`6'o01: $write("SUB");`	`6'o01: $write("SUB");`
`6'o02: $write("ADDC");`	`6'o02: $write("ADDC");`
Line 250...	Line 250...

`default: $write("XXX");`	`default: $write("XXX");`
`endcase // case (sim.rOPC_IF)`	`endcase // case (sim.rOPC_IF)`

`case (sim.rOPC_IF[3])`	`case (sim.rOPC_IF[3])`
`1'b1: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);`	`1'b1: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);`
`1'b0: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF," ");`	`1'b0: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF," ");`
`endcase // case (sim.rOPC_IF[3])`	`endcase // case (sim.rOPC_IF[3])`

`if (sim.bpcu.fHZD)`	`if (sim.bpcu.fHZD)`
`$write ("*");`	`$write ("*");`

`// ALU`	`// ALU`
`$write("\t\|");`	`$write("\t\|");`
`$writeh(" A=",sim.rOPA_OF);`	`$write(" A=",sim.rOPA_OF);`
`$writeh(" B=",sim.rOPB_OF);`	`$write(" B=",sim.rOPB_OF);`
`$writeh(" C=",sim.rOPX_OF);`	`$write(" C=",sim.rOPX_OF);`
`$writeh(" M=",sim.rOPM_OF);`	`$write(" M=",sim.rOPM_OF);`

`$writeh(" MSR=", wMSR," ");`	`$write(" MSR=", wMSR," ");`

`case (sim.rALU_OF)`	`case (sim.rALU_OF)`
`3'o0: $write(" ADD");`	`3'o0: $write(" ADD");`
`3'o1: $write(" BSF");`	`3'o1: $write(" BSF");`
`3'o2: $write(" SLM");`	`3'o2: $write(" SLM");`
Line 277...	Line 277...
`endcase // case (sim.rALU_OF)`	`endcase // case (sim.rALU_OF)`

`// MA`	`// MA`
`$write ("\t\| ");`	`$write ("\t\| ");`
`if (sim.dwb_stb_o)`	`if (sim.dwb_stb_o)`
`$writeh("@",sim.rRES_EX);`	`$write("@",sim.rRES_EX);`
`else`	`else`
`$writeh("=",sim.rRES_EX);`	`$write("=",sim.rRES_EX);`


`case (sim.rBRA)`	`case (sim.rBRA)`
`2'b00: $write(" ");`	`2'b00: $write(" ");`
`2'b01: $write(".");`	`2'b01: $write(".");`
Line 295...	Line 295...
`$write("\t\|");`	`$write("\t\|");`

`if (\|sim.rRD_MA) begin`	`if (\|sim.rRD_MA) begin`
`case (sim.rOPD_MA)`	`case (sim.rOPD_MA)`
`2'o2: begin`	`2'o2: begin`
`if (sim.rSEL_MA != 4'h0) $writeh("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");`	`if (sim.rSEL_MA != 4'h0) $write("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");`
`if (sim.rSEL_MA == 4'h0) $writeh("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");`	`if (sim.rSEL_MA == 4'h0) $write("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");`
`end`	`end`
`2'o1: $writeh("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");`	`2'o1: $write("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");`
`2'o0: $writeh("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");`	`2'o0: $write("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");`
`endcase // case (sim.rOPD_MA)`	`endcase // case (sim.rOPD_MA)`
`end`	`end`

`/*`	`/*`
`// STORE`	`// STORE`
`if (dwb_stb_o & dwb_wre_o) begin`	`if (dwb_stb_o & dwb_wre_o) begin`
`$writeh("RAM(", dwb_adr ,")=", dwb_dat_o);`	`$write("RAM(", dwb_adr ,")=", dwb_dat_o);`
`case (dwb_sel_o)`	`case (dwb_sel_o)`
`4'hF: $write(":L");`	`4'hF: $write(":L");`
`4'h3,4'hC: $write(":W");`	`4'h3,4'hC: $write(":W");`
`4'h1,4'h2,4'h4,4'h8: $write(":B");`	`4'h1,4'h2,4'h4,4'h8: $write(":B");`
`endcase // case (dwb_sel_o)`	`endcase // case (dwb_sel_o)`
Line 325...	Line 325...

`/* $Log: not supported by cvs2svn $*/`	`/* $Log: not supported by cvs2svn $*/`
`/* Revision 1.1 2007/12/18 18:54:36 sybreon*/`	`/* Revision 1.1 2007/12/18 18:54:36 sybreon*/`
`/* Partitioned simulation model.*/`	`/* Partitioned simulation model.*/`
`/* */`	`/* */`
`No newline at end of file`	`No newline at end of file`

`No newline at end of file`	`No newline at end of file`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_sim.v] - Diff between revs 16 and 48