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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB_sim.v] - Diff between revs 16 and 48

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Rev 16	Rev 48
Line 109...	Line 109...
`ifdef AEMB_SIM_KERNEL	`ifdef AEMB_SIM_KERNEL
`always @(posedge cpu.gclk) begin`	`always @(posedge cpu.gclk) begin`
`if (cpu.gena) begin`	`if (cpu.gena) begin`

`$write ("\n", ($stime/10));`	`$write ("\n", ($stime/10));`
`$writeh (" PC=", iwb_adr );`	`$write (" PC=", iwb_adr );`
`$writeh ("\t");`	`$write ("\t");`

`case (wBRA)`	`case (wBRA)`
`2'b00: $write(" ");`	`2'b00: $write(" ");`
`2'b01: $write(".");`	`2'b01: $write(".");`
`2'b10: $write("-");`	`2'b10: $write("-");`
Line 244...	Line 244...

`default: $write("XXX");`	`default: $write("XXX");`
`endcase // case (cpu.rOPC)`	`endcase // case (cpu.rOPC)`

`case (cpu.rOPC[3])`	`case (cpu.rOPC[3])`
`1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM);`	`1'b1: $write("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM);`
`1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," ");`	`1'b0: $write("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," ");`
`endcase // case (cpu.rOPC[3])`	`endcase // case (cpu.rOPC[3])`


`// ALU`	`// ALU`
`$write("\t");`	`$write("\t");`
Line 263...	Line 263...
`3'o3: $write(" MOV");`	`3'o3: $write(" MOV");`
`3'o4: $write(" MUL");`	`3'o4: $write(" MUL");`
`3'o5: $write(" BSF");`	`3'o5: $write(" BSF");`
`default: $write(" XXX");`	`default: $write(" XXX");`
`endcase // case (cpu.rMXALU)`	`endcase // case (cpu.rMXALU)`
`$writeh("=h",cpu.xecu.xRESULT);`	`$write("=h",cpu.xecu.xRESULT);`

`// WRITEBACK`	`// WRITEBACK`
`$writeh("\tSR=", wMSR," ");`	`$write("\tSR=", wMSR," ");`

`if (cpu.regf.fRDWE) begin`	`if (cpu.regf.fRDWE) begin`
`case (cpu.rMXDST)`	`case (cpu.rMXDST)`
`2'o2: begin`	`2'o2: begin`
`if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")");`	`if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")");`
`if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")");`	`if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")");`
`end`	`end`
`2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")");`	`2'o1: $write("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")");`
`2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")");`	`2'o0: $write("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")");`
`endcase // case (cpu.rMXDST)`	`endcase // case (cpu.rMXDST)`
`end`	`end`

`// STORE`	`// STORE`
`if (dwb_stb_o & dwb_wre_o) begin`	`if (dwb_stb_o & dwb_wre_o) begin`
Line 305...	Line 305...
$Log: not supported by cvs2svn $	$Log: not supported by cvs2svn $
`Revision 1.1 2007/12/23 20:40:45 sybreon`	`Revision 1.1 2007/12/23 20:40:45 sybreon`
`Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.`	`Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.`

`*/`	`*/`
`No newline at end of file`	`No newline at end of file`

`No newline at end of file`	`No newline at end of file`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB_sim.v] - Diff between revs 16 and 48