URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32.v] - Diff between revs 19 and 25

Rev 19	Rev 25
Line 12...	Line 12...
`)(`	`)(`
`// ----- Inputs -------`	`// ----- Inputs -------`
`clk_i,`	`clk_i,`
`rst_i,`	`rst_i,`
`interrupt,`	`interrupt,`
	`en_i,`
`// Instruction Wishbone master`	`// Instruction Wishbone master`
`I_DAT_I,`	`I_DAT_I,`
`I_ACK_I,`	`I_ACK_I,`
`I_ERR_I,`	`I_ERR_I,`
`I_RTY_I,`	`I_RTY_I,`
Line 48...	Line 49...



`input clk_i; // Clock`	`input clk_i; // Clock`
`input rst_i; // Reset`	`input rst_i; // Reset`
	`input en_i;`


	`wire reset;`

	`assign reset = rst_i \| ~ en_i;`

//`ifdef CFG_INTERRUPTS_ENABLED	//`ifdef CFG_INTERRUPTS_ENABLED
input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins	input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
//`endif	//`endif

Line 134...	Line 141...

`wire [31:0] iadr_o,dadr_o;`	`wire [31:0] iadr_o,dadr_o;`

`lm32_top the_lm32_top(`	`lm32_top the_lm32_top(`
`.clk_i(clk_i),`	`.clk_i(clk_i),`
`.rst_i(rst_i),`	`.rst_i(reset ),`
`.interrupt_n(~interrupt),`	`.interrupt_n(~interrupt),`
`.I_DAT_I(I_DAT_I),`	`.I_DAT_I(I_DAT_I),`
`.I_ACK_I(I_ACK_I),`	`.I_ACK_I(I_ACK_I),`
`.I_ERR_I(I_ERR_I),`	`.I_ERR_I(I_ERR_I),`
`.I_RTY_I(I_RTY_I),`	`.I_RTY_I(I_RTY_I),`
Line 175...	Line 182...
`// assign dwb_adr_o[31:30] = 2'b00;`	`// assign dwb_adr_o[31:30] = 2'b00;`

`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`

`No newline at end of file`	`No newline at end of file`