URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_cpu.v] - Diff between revs 17 and 48

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Rev 17	Rev 48
Line 102...	Line 102...
`D_SEL_O,`	`D_SEL_O,`
`D_STB_O,`	`D_STB_O,`
`D_WE_O,`	`D_WE_O,`
`D_CTI_O,`	`D_CTI_O,`
`D_LOCK_O,`	`D_LOCK_O,`
`D_BTE_O`	`D_BTE_O,`

	`snoop_adr_i,`
	`d_snoop_valid`


`);`	`);`

`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`
`// Parameters`	`// Parameters`
`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`
Line 276...	Line 281...
`output D_LOCK_O; // Date Wishbone interface lock bus`	`output D_LOCK_O; // Date Wishbone interface lock bus`
`wire D_LOCK_O;`	`wire D_LOCK_O;`
output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type	output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] D_BTE_O;	wire [`LM32_BTYPE_RNG] D_BTE_O;


	`input [31:0] snoop_adr_i;`
	`input d_snoop_valid;`

`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`
`// Internal nets and registers`	`// Internal nets and registers`
`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`

`// Pipeline registers`	`// Pipeline registers`
Line 899...	Line 908...
`.d_sel_o (D_SEL_O),`	`.d_sel_o (D_SEL_O),`
`.d_stb_o (D_STB_O),`	`.d_stb_o (D_STB_O),`
`.d_we_o (D_WE_O),`	`.d_we_o (D_WE_O),`
`.d_cti_o (D_CTI_O),`	`.d_cti_o (D_CTI_O),`
`.d_lock_o (D_LOCK_O),`	`.d_lock_o (D_LOCK_O),`
`.d_bte_o (D_BTE_O)`	`.d_bte_o (D_BTE_O),`

	`.snoop_adr_i (snoop_adr_i),`
	`.d_snoop_valid (d_snoop_valid)`

`);`	`);`

`// Adder`	`// Adder`
`lm32_adder adder (`	`lm32_adder adder (`
`// ----- Inputs -------`	`// ----- Inputs -------`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_cpu.v] - Diff between revs 17 and 48