URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_load_store_unit.v] - Diff between revs 17 and 48

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Rev 17	Rev 48
Line 72...	Line 72...
`d_sel_o,`	`d_sel_o,`
`d_stb_o,`	`d_stb_o,`
`d_we_o,`	`d_we_o,`
`d_cti_o,`	`d_cti_o,`
`d_lock_o,`	`d_lock_o,`
`d_bte_o`	`d_bte_o,`
	`snoop_adr_i,`
	`d_snoop_valid`
`);`	`);`

`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`
`// Parameters`	`// Parameters`
`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`
Line 163...	Line 165...
`output d_lock_o; // Date Wishbone interface lock bus`	`output d_lock_o; // Date Wishbone interface lock bus`
`wire d_lock_o;`	`wire d_lock_o;`
output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type	output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] d_bte_o;	wire [`LM32_BTYPE_RNG] d_bte_o;


	`input [31:0] snoop_adr_i;`
	`input d_snoop_valid;`

`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`
`// Internal nets and registers`	`// Internal nets and registers`
`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`

`// Microcode pipeline registers - See inputs for description`	`// Microcode pipeline registers - See inputs for description`
Line 276...	Line 282...
`.stall_request (dcache_stall_request),`	`.stall_request (dcache_stall_request),`
`.restart_request (dcache_restart_request),`	`.restart_request (dcache_restart_request),`
`.refill_request (dcache_refill_request),`	`.refill_request (dcache_refill_request),`
`.refill_address (dcache_refill_address),`	`.refill_address (dcache_refill_address),`
`.refilling (dcache_refilling),`	`.refilling (dcache_refilling),`
`.load_data (dcache_data_m)`	`.load_data (dcache_data_m),`
	`.snoop_adr_i (snoop_adr_i),`
	`.d_snoop_valid (d_snoop_valid)`

`);`	`);`
`endif	`endif

`/////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////`
`// Combinational Logic`	`// Combinational Logic`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_load_store_unit.v] - Diff between revs 17 and 48