URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_simtrace.v] - Diff between revs 34 and 38

Rev 34	Rev 38
Line 6...	Line 6...
`// Dependencies : lm32_include.v`	`// Dependencies : lm32_include.v`
`// Version : soc-lm32 only`	`// Version : soc-lm32 only`
`// =============================================================================`	`// =============================================================================`

`include "lm32_include.v"	`include "lm32_include.v"
	`define DISPLAY_INST 0

`// Index of opcode field in an instruction`	`// Index of opcode field in an instruction`
`define LM32_OPCODE_RNG 31:26	`define LM32_OPCODE_RNG 31:26
`define LM32_OP_RNG 30:26	`define LM32_OP_RNG 30:26

Line 83...	Line 84...
`instruction_x <= instruction_d;`	`instruction_x <= instruction_d;`
if (stall_m == `FALSE)	if (stall_m == `FALSE)
`instruction_m <= instruction_x;`	`instruction_m <= instruction_x;`
`instruction <= instruction_m;`	`instruction <= instruction_m;`

if ((valid_w == `TRUE) && (!kill_w)) begin	if ((valid_w == `TRUE) && (!kill_w) && `DISPLAY_INST) begin
`// $write ( $stime/10 );`	`// $write ( $stime/10 );`
`//$writeh( " [", pc_w << 2);`	`//$writeh( " [", pc_w << 2);`
`//$writeh( "]\t" );`	`//$writeh( "]\t" );`
`$write ( " [0x%h]\t", pc_w << 2);`	`$write ( " [0x%h]\t", pc_w << 2);`
case ( instruction[`LM32_OPCODE_RNG] )	case ( instruction[`LM32_OPCODE_RNG] )