OpenCores
URL https://opencores.org/ocsvn/ao68000/ao68000/trunk

Subversion Repositories ao68000

[/] [ao68000/] [trunk/] [doc/] [doxygen/] [html/] [classmemory__registers-members.html] - Diff between revs 15 and 16

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 15 Rev 16
Line 29... Line 29...
  <div class="headertitle">
  <div class="headertitle">
<h1>memory_registers Member List</h1>  </div>
<h1>memory_registers Member List</h1>  </div>
</div>
</div>
<div class="contents">
<div class="contents">
This is the complete list of members for <a class="el" href="classmemory__registers.html">memory_registers</a>, including all inherited members.<table>
This is the complete list of members for <a class="el" href="classmemory__registers.html">memory_registers</a>, including all inherited members.<table>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a4d664c63ba14fa2b1664eb44203191fa">clock</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a431adf2f23f5aaf563824a502920385e">reset_n</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a8d14d4f6f8c5706382c7f69b9e372660">An_address</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#ada61c344785639f1dff0853342ffc0e2">An_input</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a388c5aa2ed803d7f8fe0de1afc4ce0b3">An_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#ad83e80e6d6181078383f523cd155b88d">An_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#aa2114065af0aee3f968f55ab8d0cdd32">usp</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a452091de9055b5a8c4b3a24f832bbff4">Dn_address</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a648512e0b41016edfe8de5136ddd1c06">Dn_input</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#afca18b6c4dc049b6c423a8bec09d6d76">Dn_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a71a1a19e94fca451263e5f59daf32bbc">Dn_size</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a992b24ce3987b39fc0bd77a602b8501c">Dn_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a9d473ab60fc9c54280c725306fd4a60e">micro_pc</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a6b80d6fab3ba246fa01c780bd1754229">micro_data</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a6b262496d8e72511014d422843dc16cb">An_ram_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a3d04ddf3e78cabbf0585da3688abb8b1">An_ram_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#af880499b12dc0f4afad0fdf7500bc3bf">dn_byteena</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">ALWAYS_29</a>clock, reset_n</td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Always Construct]</code></td></tr>
  <tr class="memlist"><td><a class="el" href="classmemory__registers.html#a833db0d5eda614d712b846b259c0f4d3">ALWAYS_30</a>clock, reset_n</td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Always Construct]</code></td></tr>
</table></div>
</table></div>
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 17:55:18 for ao68000 by&#160;
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 22:20:15 for ao68000 by&#160;
<a href="http://www.doxygen.org/index.html">
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
</body>
</body>
</html>
</html>
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.