| Line 90... |
Line 90... |
-- data with increment +1 is used to verify the input data.
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-- data with increment +1 is used to verify the input data.
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-- When g_use_steps=TRUE then the g_nof_steps =
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-- When g_use_steps=TRUE then the g_nof_steps =
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-- c_diag_seq_rx_reg_nof_steps = 4 MM step registers define the allowed
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-- c_diag_seq_rx_reg_nof_steps = 4 MM step registers define the allowed
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-- COUNTER increment values.
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-- COUNTER increment values.
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, mm_lib, common_ram_lib;
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, astron_mm_lib, astron_ram_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE astron_ram_lib.common_ram_pkg.ALL;
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USE mm_lib.common_field_pkg.ALL;
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USE astron_mm_lib.common_field_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE work.diag_pkg.ALL;
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USE work.diag_pkg.ALL;
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|
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ENTITY mms_diag_rx_seq IS
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ENTITY mms_diag_rx_seq IS
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GENERIC (
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GENERIC (
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| Line 267... |
Line 267... |
stat_reg_arr(I)( 1+1*c_word_w) <= stat_res_val_n_arr(I); -- address 1, data bit [1]
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stat_reg_arr(I)( 1+1*c_word_w) <= stat_res_val_n_arr(I); -- address 1, data bit [1]
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stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= rx_cnt_arr(I); -- address 2: read rx_cnt per stream
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stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= rx_cnt_arr(I); -- address 2: read rx_cnt per stream
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stat_reg_arr(I)(4*c_word_w-1 DOWNTO 3*c_word_w) <= RESIZE_UVEC(rx_sample_arr(I), c_word_w); -- address 3: read valid sample per stream
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stat_reg_arr(I)(4*c_word_w-1 DOWNTO 3*c_word_w) <= RESIZE_UVEC(rx_sample_arr(I), c_word_w); -- address 3: read valid sample per stream
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END PROCESS;
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END PROCESS;
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u_reg : ENTITY mm_lib.common_reg_r_w_dc
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u_reg : ENTITY astron_mm_lib.common_reg_r_w_dc
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GENERIC MAP (
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GENERIC MAP (
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g_cross_clock_domain => TRUE,
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g_cross_clock_domain => TRUE,
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g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
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g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
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g_reg => c_mm_reg
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g_reg => c_mm_reg
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)
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)
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| Line 291... |
Line 291... |
out_reg => ctrl_reg_arr(I)
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out_reg => ctrl_reg_arr(I)
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);
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);
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END GENERATE;
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END GENERATE;
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|
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-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
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-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
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u_mem_mux : ENTITY mm_lib.common_mem_mux
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u_mem_mux : ENTITY astron_mm_lib.common_mem_mux
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GENERIC MAP (
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GENERIC MAP (
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g_nof_mosi => g_nof_streams,
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g_nof_mosi => g_nof_streams,
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g_mult_addr_w => c_mm_reg.adr_w
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g_mult_addr_w => c_mm_reg.adr_w
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)
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)
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PORT MAP (
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PORT MAP (
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