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-- Engineer : RyuShinHyung
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-- Engineer : RyuShinHyung
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--
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--
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-- Create Date : 02/23/2005
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-- Create Date : 02/23/2005
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-- Design Name :
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-- Design Name :
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-- Module Name : ENC8B10B - RTL
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-- Module Name : ENC8B10B - RTL
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-- Project Name : DSP Application
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-- Project Name : Fiber Optic Application
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--
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--
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-- Revision
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-- Revision
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created.
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-- Comments : General ENC8B10B
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-- 1.00 - publishing on the opencores.org.
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-- 1.01 - eliminate needing the VECTLIB.vhd in the original revision.(20110424)
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.vect_pack.ALL;
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entity ENC8B10B is
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entity ENC8B10B is
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port
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port
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(
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(
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CLK_IN : in STD_LOGIC;
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CLK_IN : in STD_LOGIC;
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Line 26... |
CTRL_IN : in STD_LOGIC;
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CTRL_IN : in STD_LOGIC;
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DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
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DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
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RUNDP_OUT : out STD_LOGIC;
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RUNDP_OUT : out STD_LOGIC;
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ENCODE_OUT : out STD_LOGIC_VECTOR(9 downto 0)
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ENCODE_OUT : out STD_LOGIC_VECTOR(9 downto 0)
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);
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);
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attribute FAST : string;
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attribute SLOW : string;
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attribute FAST of ENC8B10B : entity is "TRUE";
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attribute SLOW of ENC8B10B : entity is "FALSE";
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end ENC8B10B;
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end ENC8B10B;
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architecture RTL of ENC8B10B is
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architecture RTL of ENC8B10B is
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type TYPE_ENC8b10b is array (0 to 1023) of std_logic_vector (10 downto 0); -- RD & Dx.y
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type TYPE_ENC8b10b is array (0 to 1023) of std_logic_vector (10 downto 0); -- RD & Dx.y
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Line 1098... |
constant DEC_K23D7 : std_logic_vector := "11110111"; -- K23.7
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constant DEC_K23D7 : std_logic_vector := "11110111"; -- K23.7
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constant DEC_K27D7 : std_logic_vector := "11111011"; -- K27.7
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constant DEC_K27D7 : std_logic_vector := "11111011"; -- K27.7
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constant DEC_K29D7 : std_logic_vector := "11111101"; -- K29.7
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constant DEC_K29D7 : std_logic_vector := "11111101"; -- K29.7
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constant DEC_K30D7 : std_logic_vector := "11111110"; -- K30.7
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constant DEC_K30D7 : std_logic_vector := "11111110"; -- K30.7
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signal ENCODE : std_logic_vector (10 downto 0);
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signal ENCODE : std_logic_vector (10 downto 0);
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begin
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begin
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RUNDP_OUT <= ENCODE(10);
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RUNDP_OUT <= ENCODE(10);
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ENCODE_OUT <= ENCODE(9 downto 0);
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ENCODE_OUT <= ENCODE(9 downto 0);
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Line 1109... |
process (CLK_IN)
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process (CLK_IN)
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begin
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begin
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if (CLK_IN='1' and CLK_IN'event)
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if (CLK_IN='1' and CLK_IN'event)
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then
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then
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ENCODE <= TBL_ENC8b10b(conv_integer(CTRL_IN & ((not RUNDP_RESET_IN) and ENCODE(10)) & DATA_IN));
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ENCODE <= TBL_ENC8b10b(conv_integer(CTRL_IN & ((not RUNDP_RESET_IN) and ENCODE(10)) & DATA_IN));
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--ENCODE <=ENC_K28D5R0;
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--ENCODE <= '0' & CTRL_IN & ENCODE(10) & DATA_IN;
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end if;
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end if;
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end process;
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end process;
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end RTL;
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end RTL;
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No newline at end of file
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No newline at end of file
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