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module im (/*AUTOARG*/
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module im (/*AUTOARG*/
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// Outputs
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// Outputs
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do0, do1, do2, do3, deco, dia, do4,
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do0, do1, do2, do3, deco, dia, do4,
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// Inputs
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// Inputs
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di0, di1, di2, di3, deci, di4, doa, doa4, rst_n
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di0, di1, di2, di3, deci, di4, doa, doa4
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`ifndef ENABLE_CRRD
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, cms
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`endif
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, rst_n
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);
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);
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parameter MN = 2; // the number of CMs
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parameter MN = 2; // the number of CMs
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parameter NN = 2; // the number of IPs in one IM
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parameter NN = 2; // the number of IPs in one IM
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parameter DW = 8; // the data width of a single IP
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parameter DW = 8; // the data width of a single IP
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parameter SN = 2; // the number of possible output directions
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parameter SN = 2; // the number of possible output directions
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parameter SCN = DW/2; // the number of sub-channels in one IP
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parameter SCN = DW/2; // the number of sub-channels in one IP
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input [MN-1:0][SN-1:0] cms; // the states from CMs
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input [MN-1:0][SN-1:0] cms; // the states from CMs
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`endif
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`endif
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input rst_n; // global active low reset
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input rst_n; // global active low reset
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wire cfg; // the configuration for the IM
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wire [MN-1:0][NN-1:0] cfg; // the configuration for the IM
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wire [MN-1:0][SCN-1:0] imo0, imo1, imo2, imo3; // the IM output data
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wire [MN-1:0][SCN-1:0] imo0, imo1, imo2, imo3; // the IM output data
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wire [MN-1:0][SN-1:0] imodec; // the IM output dec
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wire [MN-1:0][SN-1:0] imodec; // the IM output dec
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][SCN-1:0] imo4; // IM output data
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wire [MN-1:0][SCN-1:0] imo4; // IM output data
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wire [MN-1:0][SCN-1:0] imoa, imoa4; // IM output ack
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wire [MN-1:0][SCN-1:0] imoa, imoa4; // IM output ack
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wire [MN-1:0][SCN-1:0] eofan, eofan, doan, deca, decan; // stage control acks
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wire [MN-1:0][SCN-1:0] eofan, doan, deca; // stage control acks
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`else
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`else
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wire [MN-1:0] imo4; // IM data output
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wire [MN-1:0] imo4; // IM data output
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wire [MN-1:0] imoa, imoa4; // IM output ack
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wire [MN-1:0] imoa, imoa4; // IM output ack
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wire [MN-1:0] eofan, eofan, doan, deca, decan; // stage control acks
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wire [MN-1:0] eofan, doan, deca; // stage control acks
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0] decan;
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genvar i;
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genvar i, j;
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// the data crossbar
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// the data crossbar
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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IMDCB (
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IMDCB (
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.o0 ( imo0 ),
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.o0 ( imo0 ),
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
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PEoF (
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.d_in_a ( ),
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.d_in_a ( ),
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.d_out ( do4[i][j] ),
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.d_out ( do4[i][j] ),
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.d_in ( imo4[i][j] ),
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.d_in ( imo4[i][j] ),
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.d_out_a ( eofa[i][j] ),
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.d_out_a ( eofan[i][j] ),
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);
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);
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ppc PCTL (
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ppc PCTL (
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.deca ( deca[i][j] ),
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.deca ( deca[i][j] ),
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.
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.dia ( imoa4[i][j] ),
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.eof ( do4[i][j] ),
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.doa ( doa[i][j] ),
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.dec ( |deco[i] )
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);
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assign doan[i][j] = (~doa[i][j])&rst_n;
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assign eofan[i][j] = (~deca[i][j])&rst_n;
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end // block: SC
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assign decan[i] = (~&deca[i])&rst_n;
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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pipe4 #(.DW(DW))
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P (
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.o0 ( do0[i] ),
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.o1 ( do1[i] ),
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.o2 ( do2[i] ),
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.o3 ( do3[i] ),
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.ia ( imoa[i] ),
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.i0 ( imo0[i] ),
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.i1 ( imo1[i] ),
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.i2 ( imo2[i] ),
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.i3 ( imo3[i] ),
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.oa ( doan[i] )
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);
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pipen #(.DW(1))
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PEoF (
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.d_in_a ( ),
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.d_out ( do4[i] ),
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.d_in ( imo4[i] ),
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.d_out_a ( eofan[i] )
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);
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ppc PCTL (
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.deca ( deca[i] ),
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.dia ( imoa4[i] ),
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.eof ( do4[i] ),
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.doa ( doa[i] ),
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.dec ( |deco[i] )
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);
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assign doan[i] = (~doa[i])&rst_n;
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assign eofan[i] = (~deca[i])&rst_n;
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assign decan[i] = (~deca[i])&rst_n;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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pipen #(.DW(SN))
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pipen #(.DW(SN))
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PDEC (
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PDEC (
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.d_in_a ( ),
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.d_out ( deco[i] ),
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.d_in ( imodec[i] ),
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.d_out_a ( decan[i] )
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);
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end // block: OPD
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endgenerate
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endmodule // im
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endmodule // im
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