| Line 141... |
Line 141... |
|
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
end // block: DP
|
end // block: DP
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endgenerate
|
endgenerate
|
|
|
generate for(i=2; i<PD; i++) begin: DPA
|
generate
|
|
for(i=2; i<PD; i++) begin: DPA
|
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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assign pd4an[i] = pdan[i];
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assign pd4an[i] = pdan[i];
|
end
|
end
|
|
|
|
// in case only one pipeline stage is configured
|
if(PD>1)
|
if(PD>1)
|
assign ia = pda[PD]|pd4[PD-1];
|
assign ia = pda[PD]|pd4[PD-1];
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else
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else
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assign ia = pda1;
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assign ia = pda1;
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|
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| Line 187... |
Line 189... |
and Py_7 (pipe_yd[7], ~rta, pd3[1][3]);
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and Py_7 (pipe_yd[7], ~rta, pd3[1][3]);
|
|
|
|
|
routing_decision // the comparator
|
routing_decision // the comparator
|
RTD(
|
RTD(
|
.addrx ( addrx )
|
.addrx ( addrx ),
|
,.addry ( addry )
|
.addry ( addry ),
|
,.pipe_xd ( pipe_xd )
|
.pipe_xd ( pipe_xd ),
|
,.pipe_yd ( pipe_yd )
|
.pipe_yd ( pipe_yd ),
|
,.decision ( raw_dec )
|
.decision ( raw_dec )
|
);
|
);
|
|
|
// translate it into the XY dec; not QDI here as the circuit can be slow
|
// translate it into the XY dec; not QDI here as the circuit can be slow
|
assign xy_dec[1:0] = raw_dec[1:0];
|
assign xy_dec[1:0] = raw_dec[1:0];
|
assign xy_dec[4:2] = raw_dec[2] ? raw_dec[5:3] : 0;
|
assign xy_dec[4:2] = raw_dec[2] ? raw_dec[5:3] : 0;
|
| Line 203... |
Line 205... |
// the decoded routing requests
|
// the decoded routing requests
|
pipen #(.DW(RN))
|
pipen #(.DW(RN))
|
PDEC (
|
PDEC (
|
.d_in_a ( rta ),
|
.d_in_a ( rta ),
|
.d_out ( dec_reg ),
|
.d_out ( dec_reg ),
|
.d_in ( raw_dec ),
|
.d_in ( xy_dec ),
|
.d_out_a ( xy_dec )
|
.d_out_a ( decan )
|
);
|
);
|
|
|
|
assign decan = ~(&deca);
|
|
|
// generate the arbiter request signals
|
// generate the arbiter request signals
|
assign deco =
|
assign deco =
|
DIR == 0 ? {dec_reg[4],dec_reg[2],dec_reg[1],dec_reg[3]} : // south port
|
DIR == 0 ? {dec_reg[4],dec_reg[2],dec_reg[1],dec_reg[3]} : // south port
|
DIR == 1 ? {dec_reg[4],dec_reg[2]} : // west port
|
DIR == 1 ? {dec_reg[4],dec_reg[2]} : // west port
|
DIR == 2 ? {dec_reg[4],dec_reg[2],dec_reg[3],dec_reg[0]} : // north port
|
DIR == 2 ? {dec_reg[4],dec_reg[2],dec_reg[3],dec_reg[0]} : // north port
|
| Line 229... |
Line 233... |
|
|
`ifdef ENABLE_CHANNEL_SLICING
|
`ifdef ENABLE_CHANNEL_SLICING
|
for(j=0; j<SCN; j++) begin: SC
|
for(j=0; j<SCN; j++) begin: SC
|
// the sub-channel controller
|
// the sub-channel controller
|
ppc SCH_C (
|
ppc SCH_C (
|
.nack ( pdan[0][j] ),
|
|
.rt_rst ( rtrst[j] ),
|
|
.ai2cb ( oa[j] ),
|
|
.ack ( pda[1][j] ),
|
|
.eof ( pd4[0][j] ),
|
|
.rt_ra ( rt_ack ),
|
|
.rt_err ( rt_err ),
|
|
.rst_n ( rst_n )
|
|
);
|
|
assign pd4an[0][j] = pdan[0][j];
|
|
|
|
ppc SCH_C (
|
|
.deca ( deca[j] ),
|
.deca ( deca[j] ),
|
.dia ( pda1[j] ),
|
.dia ( pda1[j] ),
|
.eof ( pd4[0][j] ),
|
.eof ( pd4[0][j] ),
|
.doa ( acko[j]|(pda[0][j]&rt_err) ), // to handle faulty frames
|
.doa ( acko[j]|(pda[0][j]&rt_err) ), // to handle faulty frames
|
.dec ( rta )
|
.dec ( rta )
|
);
|
);
|
|
|
|
// the lookahead pipeline
|
`ifdef ENABLE_LOOKAHEAD
|
`ifdef ENABLE_LOOKAHEAD
|
c2n CD (.q(acko[j]), .a(oa[j]), .b(pda[0][j])); // the C2N gate to avoid early withdrawal
|
c2n CD (.q(acko[j]), .a(oa[j]), .b(pda[0][j])); // the C2N gate to avoid early withdrawal
|
`else
|
`else
|
assign acko = ai2cb;
|
assign acko[j] = oa[j];
|
`endif
|
`endif
|
|
|
|
// the ack lines for the last two pipeline stages
|
|
assign pdan[0][j] = (~oa[j])&rst_n;
|
|
assign pda4n[0][j] = (~deca[j])&rst_n;
|
|
assign pdan[1][j] = (~pda1[j])&rst_n;
|
|
assign pda4n[1][j] = pdan[1][j];
|
|
|
end // block: SC
|
end // block: SC
|
`else // !`ifdef ENABLE_CHANNEL_SLICING
|
`else // !`ifdef ENABLE_CHANNEL_SLICING
|
subc_ctl SCH_C (
|
ppc SCH_C (
|
.nack ( pdan[0] ),
|
.deca ( deca ),
|
.rt_rst ( rtrst ),
|
.dia ( pda1 ),
|
.ai2cb ( oa ),
|
|
.ack ( pda[1] ),
|
|
.eof ( pd4[0] ),
|
.eof ( pd4[0] ),
|
.rt_ra ( rt_ack ),
|
.doa ( acko|(pda[0]&rt_err) ), // to handle faulty frames
|
.rt_err ( rt_err ),
|
.dec ( rta )
|
.rst_n ( rst_n )
|
|
);
|
);
|
assign pd4an[0] = pdan[0];
|
|
|
// the lookahead pipeline
|
|
`ifdef ENABLE_LOOKAHEAD
|
|
c2n CD (.q(acko), .a(oa), .b(pda[0])); // the C2N gate to avoid early withdrawal
|
|
`else
|
|
assign acko = oa;
|
|
`endif
|
|
|
|
// the ack lines for the last two pipeline stages
|
|
assign pdan[0] = (~oa)&rst_n;
|
|
assign pda4n[0] = (~deca)&rst_n;
|
|
assign pdan[1] = (~pda1)&rst_n;
|
|
assign pda4n[1] = pdan[1];
|
|
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
|
|
// the router controller part
|
|
assign rten = ~rt_ack;
|
|
assign frame_end = &rtrst;
|
|
|
|
endmodule // inp_buf
|
endmodule // inp_buf
|
|
|
|
|
// the routing decision making procedure, comparitors
|
// the routing decision making procedure, comparitors
|
