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//-----------------------------------------------------------------------------
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// Auto Baud with tracking core
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//
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// This file is part of the "auto_baud" project.
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// http://www.opencores.org/
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//
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//
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// Description: See description below (which suffices for IP core
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// specification document.)
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//
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// Copyright (C) 2002 John Clayton and OPENCORES.ORG
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source.
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// If not, download it from http://www.opencores.org/lgpl.shtml
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//
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//-----------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date : Aug. 20, 2002 Began project
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// Update: Sep. 5, 2002 copied this file from "autobaud.v"
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// Added tracking functions, and debugged them.
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// Update: Sep. 13, 2002 Added test data. Module complete, it works well.
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//
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// Description
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//-----------------------------------------------------------------------------
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// This is a state-machine driven core that measures transition intervals
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// in a particular character arriving via rs232 transmission (i.e. PC serial
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// port.) Measurements of time intervals between transitions in the received
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// character are then used to generate a baud rate clock for use in serial
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// communications back and forth with the device that originally transmitted
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// the measured character. The clock which is generated is in reality a
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// clock enable pulse, one single clock wide, occurring at a rate suitable
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// for use in serial communications. (This means that it will be generated
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// at 4x or 8x or 16x the actual measured baud rate of the received character.
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// The multiplication factor is called "CLOCK_FACTOR_PP" and is a settable
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// parameter within this module. The parameter "CLOCK_FACTOR_PP" need not
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// be a power of two, but it should be a number between 2 and 16 inclusive.)
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//
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// The particular character which is targeted for measurement and verification
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// in this module is: carriage return (CR) = 0x0d = 13.
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// This particular character was chosen because it is frequently used at the
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// end of a command line, as entered at a keyboard by a human user interacting
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// with a command interpreter. It is anticipated that the user would press
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// the "enter" key once upon initializing communications with the electronic
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// device, and the resulting carriage return character would be used for
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// determining BAUD rate, thus allowing the device to respond at the correct
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// rate, and to carry on further communications. The electronic device using
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// this "auto_baud" module adjusts its baud rate to match the baud rate of
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// the received data. This works for all baud rates, within certain limits,
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// and for all system clock rates, within certain limits.
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//
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// Received serially, the carriage return appears as the following waveform:
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// ________ __ ____ _______________
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// |__|d0|__|d2d3|________|stop
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// start d1 d4d5d6d7
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//
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// The waveform is shown with an identical "high" time and "low" time for
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// each bit. However, actual measurements taken using a logic analyzer
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// on characters received from a PC show that the times are not equal.
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// The "high" times turned out shorter, and the "low" times longer...
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// Therefore, this module attempts to average out this discrepancy by
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// measuring one low time and one high time.
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//
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// Since the transition measurements must unavoidably contain small amounts
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// of error, the measurements are made during the beginning 2 bits of
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// the received character, (that is, start bit and data bit zero).
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// Then the measurement is immediately transformed into a baud rate clock,
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// used to verify correct reception of the remaining 8 bits of the character.
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// If the entire character is not received correctly using the generated
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// baud rate, then the measurement is scrapped, and the unit goes into an
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// idle scanning mode waiting for another character to test.
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//
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// This effectively filters out characters that the unit is not interested in
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// receiving (anything that is not a carriage return.) There is a slight
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// possibility that a group of other characters could appear by random
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// chance in a configuration that resembles a carriage return closely enough
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// that the unit might accept the measurement and produce a baud clock too
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// low. But the probability of this happening is remote enough that the
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// unit is considered highly "robust" in normal use, especially when used
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// for command entry by humans. It would take a very clever user indeed, to
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// enter the correct series of characters with the correct intercharacter
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// timing needed to possibly "fool" the unit!
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//
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// (Also, the baud rate produced falls within certain limits imposed by
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// the hardware of the unit, which prevents the auto_baud unit from mistaking
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// a series of short glitches on the serial data line for a really
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// fast CR character.)
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//
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// This method of operation implies that each carriage return character
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// received will produce a correctly generated baud rate clock. Therefore,
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// each and every carriage return actually causes a new baud rate clock to
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// be produced. However, updates occur smoothly, and there should be no
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// apparent effect as an old BAUD clock is stopped and a new one started.
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// The transition is done smoothly.
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//
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// For users who desire a single measurement at the beginning of a session
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// to produce a steady baud clock during the entire session, there is a
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// slightly smaller module called "auto_baud.v" which performs a single
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// measurement, but which requires a reset pulse in order to begin measuring
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// for a new BAUD rate.
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//
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// NOTES:
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// - This module uses a counter to divide down the clk_i signal to produce the
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// baud_clk_o signal. Since the frequency of baud_clk_o is nominally
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// CLOCK_FACTOR_PP * rx_baud_rate, where "rx_baud_rate" is the baud rate
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// of the received character, then the higher you make CLOCK_FACTOR_PP, the
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// higher the generated baud_clk_o signal frequency, and hence the lower the
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// resolution of the divider. Therefore, using a lower value for the
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// CLOCK_FACTOR_PP will allow you to use a lower clk_i with this module.
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// - To set LOG2_MAX_COUNT_PP, remember (max_count*CLOCK_FACTOR_PP)/Fclk_i
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// is the maximum measurement time that can be accomodated by the circuit.
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// (where Fclk_i is the frequency of clk_i, and 1/Fclk_i is the period.)
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// Therefore, set LOG2_MAX_COUNT_PP so that the maximum measurement time
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// is at least as long as 2x the baud interval of the slowest received
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// serial data (2x because there are two bits involved in the measurement!)
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// For example, for Fclk_i = 20MHz, CLOCK_FACTOR_PP = 4 and a minimum
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// baud rate of 115,200, you would calculate:
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//
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// (max_count * CLOCK_FACTOR_PP)*1/Fclk_i >= 2/Fbaud_max
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//
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// Solving for the bit width of the max_count counter...
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//
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// LOG2_MAX_COUNT_PP >= ceil(log_base_2(max_count))
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//
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// >= ceil(log_base_2(2*Fclk_i/(Fbaud_max*CLOCK_FACTOR_PP)))
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//
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// >= ceil(log_base_2(2*20E6/(115200*4)))
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//
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// >= ceil(log_base_2(86.8))
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//
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// >= 7 bits.
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//
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// - In the above example, the maximum count would approach 87, which means
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// that a measurement error of 1 count is about (1/87)=approx. 1.15%. This
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// is an acceptable level of error for a baud rate clock. Notice that the
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// lower baud rates have an even smaller error percentage (Yes!) but that
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// they require a much larger measurement counter... For instance,
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// to lock onto 300 baud using the same example above, would require:
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//
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// LOG2_MAX_COUNT_PP >= ceil(log_base_2(40000000/1200))
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//
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// >= ceil(log_base_2(33333.3))
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//
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// >= ceil(15.024678)
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//
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// >= 16 bits.
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//
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// - If the percentage error for your highest desired baud rate is greater
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// than a few percent, you might want to use a higher Fclk_i or else a
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// lower CLOCK_FACTOR_PP.
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//
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// - Using the default settings: CLK_FACTOR_PP = 8, LOG2_MAX_COUNT_PP = 16
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// The following test results were obtained, using an actual session in
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// hyperterm, looking for correct readable character transmission both
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// directions. (Note: These tests were performed at "human interface"
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// speeds. High speed or "back-to-back" character transmission might
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// exhibit worse performance than these results.)
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//
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// Clk_i
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// Freq.
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// (MHz) 110 300 1200 2400 4800 9600 19200 57600 115200
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// ------ ---------------------------------------------------------------
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// 98 FAIL pass pass pass pass pass pass pass pass
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// 55 FAIL pass pass pass pass pass pass pass pass
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// 49 pass pass pass pass pass pass pass pass pass
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// 24.5 pass pass pass pass pass pass pass pass FAIL
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// 12 pass pass pass pass pass pass pass pass FAIL
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// 6 pass pass pass pass pass pass pass FAIL FAIL
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// 3 pass pass pass pass pass FAIL FAIL FAIL FAIL
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// 1.5 pass pass pass pass FAIL FAIL FAIL FAIL FAIL
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//
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//
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//-------------------------------------------------------------------------------------
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`define LOG2_MAX_CLOCK_FACTOR 4 // Sets the size of the CLOCK_FACTOR
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// prescaler.
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`define BITS_PER_CHAR 8 // Include parity, if used, but not
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// start and stop bits...
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// Note: Simply changing the template bits does not reconfigure the
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// module to look for a different character (because a new measurement
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// window would have to be defined for a different character...)
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// The template bits are the exact bits used during verify, against
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// which the incoming character is checked.
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// The LSB of the character is discarded, and the stop bit is appended
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// since it is the last bit used during verify.
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//
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// so, for N:8:1 (no parity, 8 data bits, 1 stop bit) it is:
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// = {1,(character>>1)} = 9'h086
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// or, with parity included it is:
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// = {1,parity_bit,(character>>1)} = 9'h106
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//
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`define TEMPLATE_BITS 9'h086 // Carriage return && termination flag
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module auto_baud_with_tracking
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(
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clk_i,
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reset_i,
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serial_dat_i,
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auto_baud_locked_o,
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baud_clk_o
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);
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// Parameters
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// CLOCK_FACTOR_PP can be from [2..16] inclusive.
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parameter CLOCK_FACTOR_PP = 8; // Baud clock multiplier
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parameter LOG2_MAX_COUNT_PP = 16; // Bit width of measurement counter
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// State encodings, provided as parameters
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// for flexibility to the one instantiating the module.
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// In general, the default values need not be changed.
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// There is one state machines: m1.
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// "default" state upon power-up and configuration is:
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// "m1_idle" because that is the all zero state.
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parameter m1_idle = 4'h0; // Initial state (scanning)
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parameter m1_measure_0 = 4'h1; // start bit (measuring)
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parameter m1_measure_1 = 4'h2; // debounce (measuring)
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parameter m1_measure_2 = 4'h3; // data bit 0 (measuring)
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parameter m1_measure_3 = 4'h4; // debounce (measuring)
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parameter m1_measure_4 = 4'h5; // measurement done (headed to verify)
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parameter m1_verify_0 = 4'h8; // data bit 1 (verifying)
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parameter m1_verify_1 = 4'h9; // data bit 2 (verifying)
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parameter m1_run = 4'h6; // running
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parameter m1_verify_failed = 4'h7; // resetting (headed back to idle)
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// I/O declarations
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input clk_i; // System clock input
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input reset_i; // Reset signal for this module
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input serial_dat_i; // TTL level serial data signal
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output auto_baud_locked_o; // Indicates BAUD clock is being generated
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output baud_clk_o; // BAUD clock output (actually a clock enable)
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// Internal signal declarations
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wire mid_bit_count; // During measurement, advances measurement counter
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// (Using the mid bit time to advance the
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// measurement timer accomplishes a timing "round"
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// so that the timing measurement is as accurate
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// as possible.)
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// During verify, pulses at mid bit time are used
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// to signal the state machine to check a data bit.
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wire main_count_rollover; // Causes main_count to reset
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wire baud_count_rollover; // Causes baud_count to reset
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wire clock_count_rollover; // Causes clock_count to reset
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// (when clock_count is used as a
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// clock_factor prescaler)
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wire enable_clock_count; // Logic that determines when clock_count
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// should be counting
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wire verify_done; // Indicates finish of verification time
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reg idle; // Indicates state
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reg measure; // Indicates state
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reg clear_counters; // Pulses once when measurement is done.
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reg verify; // Indicates state
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reg verify_good; // Indicates successful verify (pulse)
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reg character_miscompare; // Indicates character did not verify
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reg run; // flip-flop that indicates a valid output
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// is being generated.
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reg [`LOG2_MAX_CLOCK_FACTOR-1:0] clock_count; // Clock_factor prescaler,
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// and mid_bit counter.
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reg [LOG2_MAX_COUNT_PP-1:0] main_count; // Main counter register
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reg [LOG2_MAX_COUNT_PP-1:0] baud_count; // BAUD counter register
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reg [LOG2_MAX_COUNT_PP-1:0] measurement; // measurement for verify
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reg [LOG2_MAX_COUNT_PP-1:0] baud; // measurement for running
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reg [`BITS_PER_CHAR:0] target_bits; // Character bits to compare
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// (lsb is not needed, since it is used up during measurement time,
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// but the stop bit and possible parity bit are needed.)
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// For the state machine
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reg [3:0] m1_state;
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reg [3:0] m1_next_state;
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//--------------------------------------------------------------------------
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// Instantiations
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Module code
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//--------------------------------------------------------------------------
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// This is the CLOCK_FACTOR_PP prescaler and also mid_bit_count counter
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assign enable_clock_count = measure || (verify && main_count_rollover);
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always @(posedge clk_i or posedge reset_i)
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begin
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if (reset_i) clock_count <= 0;
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else if (clear_counters) clock_count <= 0;
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else if (enable_clock_count)
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begin // Must have been clk_i edge
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if (clock_count_rollover) clock_count <= 0;
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else clock_count <= clock_count + 1;
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end
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end
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// Counter rollover condition
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assign clock_count_rollover = (clock_count == (CLOCK_FACTOR_PP-1));
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// This condition signals the middle of a bit time, for use during the
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// verify stage. Also, this signal is used to advance the main count,
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// instead of "clock_count_rollover." This produces an effective "rounding"
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// operation for the measurement (which would otherwise "truncate" any
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// fraction of time contained in this counter at the instant the measurement
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// is finished.
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// (The "enable_clock_count" is included in order to make the pulse narrow,
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// only one clock wide...)
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assign mid_bit_count = (
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(clock_count == ((CLOCK_FACTOR_PP>>1)-1))
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&& enable_clock_count
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);
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// This is the main counter. During measurement, it advances once for
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// each CLOCK_FACTOR_PP cycles of clk_i. This accumulated measurement
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// is then latched into "measurement" when the state machine determines that
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// the measurement interval is finished.
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// During verify time (when the new candidate baud rate clock is being tested)
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// this counter is allowed to run freely, advancing once each clk_i, but being
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// reset when it reaches a total count of "measurement" clock cycles.
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always @(posedge clk_i or posedge reset_i)
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begin
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if (reset_i) main_count <= 0;
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else // must have been clk_i edge
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begin
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// Clear main count when measurement is done
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if (clear_counters) main_count <= 0;
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// If measuring, advance once per CLOCK_FACTOR_PP clk_i pulses.
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else if (measure && mid_bit_count) main_count <= main_count + 1;
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// If verifying or running, check reset conditions,
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// otherwise advance always.
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else if (verify)
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begin
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if (main_count_rollover) main_count <= 0;
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else main_count <= main_count + 1;
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end
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end
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end
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// This is the "verify" baud clock signal... not the final output one.
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assign main_count_rollover = (main_count == measurement);
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// This is the BAUD counter. Once a measurement has been verified, it is
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// stored in "baud" and the signal "run" goes high. From then on, this
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// counter is allowed to run freely, advancing once each clk_i, but being
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// reset when it reaches a total count of "baud" clock cycles. This
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// counter's reset signal is the output baud rate clock.
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always @(posedge clk_i or posedge reset_i)
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begin
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if (reset_i) baud_count <= 0;
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else // must have been clk_i edge
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begin
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// If running, advance freely
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if (run)
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begin
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if (baud_count_rollover) baud_count <= 0;
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else baud_count <= baud_count + 1;
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end
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end
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end
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assign baud_count_rollover = (baud_count == baud);
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// This is a shift register used to provide "target" character bits one at
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// a time for verification as they are "received" (sampled) using the
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// candidate baud clock.
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always @(posedge clk_i or posedge reset_i)
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begin
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if (reset_i) target_bits <= `TEMPLATE_BITS;
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else // must have been a clock edge
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begin
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if (~verify) target_bits <= `TEMPLATE_BITS;
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if (verify && mid_bit_count) target_bits <= {0,(target_bits>>1)};
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end
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end
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// It is done when only the stop bit is left in the shift register.
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assign verify_done = (
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(target_bits == 1)
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&& verify
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&& mid_bit_count
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);
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// This is a flip-flop used to keep track of whether the verify operation
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// is succeeding or not. Any target bits that do not match the received
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// data at the sampling edge, will cause the verify_failed bit to go high.
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// This is what the state machine looks at to determine whether it passed
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// or not.
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always @(posedge clk_i or posedge reset_i)
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begin
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if (reset_i) character_miscompare <= 0;
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else // Must have been a clock edge
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begin
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if (idle) character_miscompare <= 0;
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if (verify && mid_bit_count
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&& (target_bits[0] ^ serial_dat_i)) character_miscompare <= 1;
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end
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end
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// This is the measurement storage latch. The final measured time count
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// from main_count is stored in this latch upon completion of the measurement
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// interval. The value stored in this latch is used for the baud clock
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// generated during verify, but a different register holds the actual value
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// being used to generate output.
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always @(posedge clk_i or posedge idle)
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begin
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// Set to all ones during idle (asynchronous).
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if (idle) measurement <= -1;
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// Otherwise, there must have been a clk_i edge
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// When the measurement is done, the counters are cleared, and the time
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// interval must be stored before it is cleared away...
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// This also causes a store following a failed verify state on the way back
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// into idle, but the idle state clears out the false measurement anyway.
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else if (clear_counters) measurement <= (main_count>>1);
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end
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// This is the BAUD storage latch. The final verified time count
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// from the "measurement" register is stored in this register after a good
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// verify. The value stored in this latch is used in conjunction with
|
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// baud_count to produce the baud clock which is sent to the output.
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always @(posedge clk_i or posedge reset_i)
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begin
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// Set to all ones during reset (asynchronous).
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if (reset_i) baud <= -1;
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// Otherwise, there must have been a clk_i edge
|
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// When the measurement is done, the counters are cleared, and the time
|
|
// interval must be stored before it is cleared away...
|
|
// This also causes a store following a failed verify state on the way back
|
|
// into idle, but the idle state clears out the false measurement anyway.
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|
else if (verify_good) baud <= measurement;
|
|
end
|
|
|
|
// This is a flip-flop used to keep track of whether the unit is producing
|
|
// a baud clock or not. Initially following reset, there is no baud clock
|
|
// being produced. But, once a single measurement is verified, then the
|
|
// clock is produced and tracking changes are made over time. Thus, this
|
|
// bit goes high as a result of the first "verify_good" pulse, and it remains
|
|
// high forever, until the unit is reset.
|
|
always @(posedge clk_i or posedge reset_i)
|
|
begin
|
|
if (reset_i) run <= 0;
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|
else // Must have been a clock edge
|
|
begin
|
|
if (verify_good) run <= 1;
|
|
end
|
|
end
|
|
|
|
assign baud_clk_o = baud_count_rollover;
|
|
|
|
|
|
// This is state machine m1. It checks the status of the serial_dat_i line
|
|
// and coordinates the measurement of the time interval of the first two
|
|
// bits of the received character, which is the "measurement interval."
|
|
// Following the measurement interval, the state machine enters a new
|
|
// phase of bit verification. If the measured time interval is accurate
|
|
// enough to measure the remaining 8 bits of the character correctly, then
|
|
// the measurement is accepted, and the baud rate clock is driven onto
|
|
// the baud_clk_o output pin. Incidentally, the process of verification
|
|
// effectively filters out all characters which are not the desired target
|
|
// character for measurement. In this case, the target character is the
|
|
// carriage return.
|
|
|
|
|
|
// State register
|
|
always @(posedge clk_i or posedge reset_i)
|
|
begin : m1_state_register
|
|
if (reset_i) m1_state <= m1_idle; // asynchronous reset
|
|
else m1_state <= m1_next_state;
|
|
end
|
|
|
|
// State transition logic
|
|
always @(m1_state
|
|
or mid_bit_count
|
|
or serial_dat_i
|
|
or verify_done
|
|
or character_miscompare
|
|
)
|
|
begin : m1_state_logic
|
|
|
|
// Default values for outputs. The individual states can override these.
|
|
idle <= 1'b0;
|
|
verify_good <= 1'b0;
|
|
measure <= 1'b0;
|
|
clear_counters <= 1'b0;
|
|
verify <= 1'b0;
|
|
|
|
case (m1_state) // synthesis parallel_case
|
|
|
|
m1_idle :
|
|
begin
|
|
idle <= 1'b1;
|
|
if (serial_dat_i == 0) m1_next_state <= m1_measure_0;
|
|
else m1_next_state <= m1_idle;
|
|
end
|
|
|
|
m1_measure_0 :
|
|
begin
|
|
measure <= 1'b1;
|
|
// Check at mid bit time, to make sure serial line is still low...
|
|
// (At this time, "mid_bit_count" is simply CLOCK_FACTOR_PP>>1 clk_i's.)
|
|
if (mid_bit_count && ~serial_dat_i) m1_next_state <= m1_measure_1;
|
|
// If it is not low, then it must have been a "glitch"...
|
|
else if (mid_bit_count && serial_dat_i) m1_next_state <= m1_idle;
|
|
else m1_next_state <= m1_measure_0;
|
|
end
|
|
|
|
m1_measure_1 :
|
|
begin
|
|
measure <= 1'b1;
|
|
// Look for first data bit (high).
|
|
if (serial_dat_i) m1_next_state <= m1_measure_2;
|
|
// If it is not high keep waiting...
|
|
// (Put detection of measurement overflow in here if necessary...)
|
|
else m1_next_state <= m1_measure_1;
|
|
end
|
|
|
|
m1_measure_2 :
|
|
begin
|
|
measure <= 1'b1;
|
|
// Check using mid bit time, to make sure serial line is still high...
|
|
// (At this time, "mid_bit_count" is simply CLOCK_FACTOR_PP>>1 clk_i's.)
|
|
if (mid_bit_count && serial_dat_i) m1_next_state <= m1_measure_3;
|
|
// If it is not high, then it must have been a "glitch"...
|
|
else if (mid_bit_count && ~serial_dat_i) m1_next_state <= m1_idle;
|
|
else m1_next_state <= m1_measure_2;
|
|
end
|
|
|
|
m1_measure_3 :
|
|
begin
|
|
measure <= 1'b1;
|
|
// Look for end of measurement interval (low)
|
|
if (!serial_dat_i) m1_next_state <= m1_measure_4;
|
|
// If it is not high keep waiting...
|
|
// (Put detection of measurement overflow in here if necessary...)
|
|
else m1_next_state <= m1_measure_3;
|
|
end
|
|
|
|
// This state outputs a reset pulse, to clear counters and store the
|
|
// measurement from main_count.
|
|
m1_measure_4 :
|
|
begin
|
|
clear_counters <= 1'b1; // Clears counters, stores measurement
|
|
m1_next_state <= m1_verify_0;
|
|
end
|
|
|
|
m1_verify_0 : // Wait for verify operations to finish
|
|
begin
|
|
verify <= 1'b1;
|
|
if (verify_done) m1_next_state <= m1_verify_1;
|
|
else m1_next_state <= m1_verify_0;
|
|
end
|
|
|
|
// NOTE: This "extra" state is needed because the character_miscompare
|
|
// information is not valid until 1 cycle after verify_done is
|
|
// active.
|
|
m1_verify_1 : // Checks for character miscompare
|
|
begin
|
|
if (character_miscompare) m1_next_state <= m1_verify_failed;
|
|
else m1_next_state <= m1_run;
|
|
end
|
|
|
|
m1_verify_failed : // Resets counters on the way back to idle
|
|
begin
|
|
clear_counters <= 1'b1;
|
|
m1_next_state <= m1_idle;
|
|
end
|
|
|
|
// This state is for successful verification results!
|
|
// Since this is a tracking unit, the "run" output is used as a pulse
|
|
// to store the now verified rate.
|
|
m1_run :
|
|
begin
|
|
verify_good <= 1'b1;
|
|
m1_next_state <= m1_idle;
|
|
end
|
|
|
|
default : m1_next_state <= m1_idle;
|
|
endcase
|
|
end
|
|
|
|
|
|
assign auto_baud_locked_o = run;
|
|
|
|
|
|
endmodule
|
|
|
|
//`undef LOG2_MAX_CLOCK_FACTOR
|
|
|
No newline at end of file
|
No newline at end of file
|
