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Line 69... |
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architecture rtl of axiBfmMaster is
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architecture rtl of axiBfmMaster is
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/* Finite-state Machines. */
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/* Finite-state Machines. */
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
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/* BFM signalling. */
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/* BFM signalling. */
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signal i_readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
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signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
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Line 88... |
outstandingTransactions<=symbolsPerTransfer;
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outstandingTransactions<=symbolsPerTransfer;
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report "No more pending transactions." severity note;
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report "No more pending transactions." severity note;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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end if;
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end if;
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end if;
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end if;
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/* debug only. */
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/*if falling_edge(aclk) then
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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else
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if outstandingTransactions<1 then
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outstandingTransactions<=symbolsPerTransfer;
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report "No more pending transactions." severity note;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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end if;
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end if;
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end if;
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*/
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end process;
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end process;
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_ns: process(all) is begin
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axi_bfmTx_ns: process(all) is begin
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axiTxState<=next_axiTxState;
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axiTxState<=next_axiTxState;
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if not n_areset then axiTxState<=idle; end if;
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if not n_areset then axiTxState<=idle;
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else
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
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if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
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when payload=>
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when payload=>
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if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
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if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
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when endOfTx=>
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when endOfTx=>
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axiTxState<=idle;
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axiTxState<=idle;
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when others=>axiTxState<=idle;
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when others=>axiTxState<=idle;
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end case;
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end case;
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end if;
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end process axi_bfmTx_ns;
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end process axi_bfmTx_ns;
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/* output logic for AXI4-Stream Master Tx BFM. */
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/* output logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_op: process(all) is begin
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axi_bfmTx_op: process(all) is begin
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i_writeResponse<=writeResponse;
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i_writeResponse<=writeResponse;
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axiMaster_out.tValid<=false;
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i_axiMaster_out.tValid<=false;
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axiMaster_out.tLast<=false;
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i_axiMaster_out.tLast<=false;
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axiMaster_out.tData<=(others=>'Z');
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i_axiMaster_out.tData<=(others=>'Z');
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i_writeResponse.trigger<=false;
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i_writeResponse.trigger<=false;
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if writeRequest.trigger xor i_writeRequest.trigger then
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tValid<=true;
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end if;
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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if writeRequest.trigger xor i_writeRequest.trigger then
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/* if writeRequest.trigger xor i_writeRequest.trigger then
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axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tValid<=true;
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i_axiMaster_out.tValid<=true;
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end if;
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end if;
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*/
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null;
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when payload=>
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when payload=>
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axiMaster_out.tValid<=true;
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i_axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tValid<=true;
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if axiMaster_in.tReady then
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if axiMaster_in.tReady then
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i_writeResponse.trigger<=true;
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i_writeResponse.trigger<=true;
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end if;
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end if;
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/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
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/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
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if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
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if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
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when others=> null;
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when others=> null;
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end case;
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end case;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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axiMaster_out<=i_axiMaster_out;
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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process(n_areset,aclk) is begin
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process(n_areset,aclk) is begin
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if not n_areset then next_axiTxState<=idle;
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--if not n_areset then next_axiTxState<=idle;
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elsif falling_edge(aclk) then
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if falling_edge(aclk) then
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next_axiTxState<=axiTxState;
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next_axiTxState<=axiTxState;
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i_writeRequest<=writeRequest;
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i_writeRequest<=writeRequest;
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--axiMaster_out<=i_axiMaster_out;
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end if;
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end if;
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end process;
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end process;
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process(aclk) is begin
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process(aclk) is begin
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if rising_edge(aclk) then
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if rising_edge(aclk) then
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