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Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [axi4-stream-bfm-master.vhdl] - Diff between revs 15 and 16

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Rev 15 Rev 16
Line 54... Line 54...
--              /* AXI Slave interface */
--              /* AXI Slave interface */
--              axiSlave_in:in tAxi4Transactor_m2s;
--              axiSlave_in:in tAxi4Transactor_m2s;
--              axiSlave_out:buffer tAxi4Transactor_s2m;
--              axiSlave_out:buffer tAxi4Transactor_s2m;
 
 
                symbolsPerTransfer:in i_transactor.t_cnt;
                symbolsPerTransfer:in i_transactor.t_cnt;
                outstandingTransactions:buffer i_transactor.t_cnt
                outstandingTransactions:in i_transactor.t_cnt
 
 
                /* Debug ports. */
                /* Debug ports. */
--              dbg_cnt:out unsigned(9 downto 0);
--              dbg_cnt:out unsigned(9 downto 0);
--              dbg_axiRxFsm:out axiBfmStatesRx:=idle;
--              dbg_axiRxFsm:out axiBfmStatesRx:=idle;
--              dbg_axiTxFsm:out axiBfmStatesTx:=idle
--              dbg_axiTxFsm:out axiBfmStatesTx:=idle
Line 74... Line 74...
        /* BFM signalling. */
        /* BFM signalling. */
        signal i_readRequest,i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
        signal i_readRequest,i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
        signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
        signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
 
 
begin
begin
        /* Transaction counter. */
 
        process(n_areset,symbolsPerTransfer,aclk) is begin
 
                if not n_areset then outstandingTransactions<=symbolsPerTransfer;
 
                elsif falling_edge(aclk) then
 
                        if outstandingTransactions<1 then
 
                                outstandingTransactions<=symbolsPerTransfer;
 
                                report "No more pending transactions." severity note;
 
                        elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
 
                        end if;
 
                end if;
 
        end process;
 
 
 
        /* next-state logic for AXI4-Stream Master Tx BFM. */
        /* next-state logic for AXI4-Stream Master Tx BFM. */
        axi_bfmTx_ns: process(all) is begin
        axi_bfmTx_ns: process(all) is begin
                axiTxState<=next_axiTxState;
                axiTxState<=next_axiTxState;
 
 
                if not n_areset then axiTxState<=idle;
                if not n_areset then axiTxState<=idle;
Line 128... Line 116...
 
 
                                if axiMaster_in.tReady then
                                if axiMaster_in.tReady then
                                        i_writeResponse.trigger<=true;
                                        i_writeResponse.trigger<=true;
                                end if;
                                end if;
 
 
                                /* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
 
                                if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
                                if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
                        when others=> null;
                        when others=> null;
                end case;
                end case;
        end process axi_bfmTx_op;
        end process axi_bfmTx_op;
 
 

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