| Line 64... |
Line 64... |
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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signal symbolsPerTransfer:t_cnt;
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signal symbolsPerTransfer:t_cnt;
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signal outstandingTransactions:t_cnt;
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signal outstandingTransactions:t_cnt;
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/* BFM signalling. */
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/* BFM signalling. */
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signal readRequest,next_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal writeRequest,next_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal readResponse,next_readResponse:t_bfm;
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signal readResponse:t_bfm;
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signal writeResponse,next_writeResponse:t_bfm;
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signal writeResponse:t_bfm;
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk,nReset:std_ulogic:='0';
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signal clk,nReset:std_ulogic:='0';
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal trigger:boolean;
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--signal trigger:boolean;
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal anlysr_trigger:std_ulogic;
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/* Signal preservations for SignalTap II probing. */
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/* Signal preservations for SignalTap II probing. */
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attribute keep:boolean;
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--attribute keep:boolean;
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attribute keep of trigger:signal is true;
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--attribute keep of trigger:signal is true;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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begin
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begin
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/* pipelines. */
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process(clk) is begin
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if rising_edge(clk) then
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next_readRequest<=readRequest;
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next_writeRequest<=writeRequest;
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next_readResponse<=readResponse;
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next_writeResponse<=writeResponse;
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end if;
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end process;
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity work.axiBfmMaster(rtl)
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axiMaster: entity work.axiBfmMaster(rtl)
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-- generic map(maxTransactions=>maxSymbols)
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port map(
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port map(
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aclk=>irq_write, n_areset=>nReset,
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aclk=>irq_write, n_areset=>nReset,
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trigger=>irq_write='1',
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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| Line 178... |
Line 167... |
trigger_in=>anlysr_trigger
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trigger_in=>anlysr_trigger
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);
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);
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/* Stimuli sequencer. */
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/* Stimuli sequencer. TODO move to tester/stimuli.
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This emulates the AXI4-Stream Slave.
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*/
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/* Simulation-only stimuli sequencer. */
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/* synthesis translate_off */
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process is begin
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/* Fast read. */
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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end loop;
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wait until falling_edge(clk);
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/* Normal read. */
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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end loop;
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for i in 0 to 10 loop
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wait until falling_edge(clk);
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end loop;
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/* One-shot read. */
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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wait;
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end process;
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/* synthesis translate_on */
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/* Synthesisable stimuli sequencer. */
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axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
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axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
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/* Data transmitter. */
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sequencer: process(nReset,irq_write) is
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sequencer: process(nReset,irq_write) is
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/* Local procedures to map BFM signals with the package procedure. */
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/* Local procedures to map BFM signals with the package procedure. */
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procedure read(address:in t_addr) is begin
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procedure read(address:in t_addr) is begin
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read(readRequest,address);
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read(readRequest,address);
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end procedure read;
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end procedure read;
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| Line 195... |
Line 234... |
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variable isPktError:boolean;
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variable isPktError:boolean;
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/* Tester variables. */
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/* Tester variables. */
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/* Synthesis-only randomisation. */
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/* Synthesis-only randomisation. */
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variable seed0,seed1:positive:=1;
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--variable rand0:real;
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variable rand0:signed(63 downto 0);
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variable rand0:signed(63 downto 0);
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/* Simulation-only randomisation. */
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/* Simulation-only randomisation. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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variable rv0,rv1:RandomPType;
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variable rv0:RandomPType;
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/* synthesis translate_on */
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/* synthesis translate_on */
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begin
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begin
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if not nReset then
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if not nReset then
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/* synthesis only. */
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/* synthesis only. */
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seed0:=1; seed1:=1;
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--uniform(seed0,seed1,rand0);
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rand0:=(others=>'0');
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rand0:=(others=>'0');
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--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);
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symbolsPerTransfer<=128x"8";
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/* simulation only. */
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/* simulation only. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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rv0.InitSeed(rv0'instance_name);
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rv1.InitSeed(rv1'instance_name);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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/* synthesis translate_on */
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/* synthesis translate_on */
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txFSM<=idle;
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elsif falling_edge(irq_write) then
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elsif falling_edge(irq_write) then
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--write(64x"abcd1234");
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case txFSM is
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when idle=>
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if outstandingTransactions>0 then
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if outstandingTransactions>0 then
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/* synthesis only. */
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/* synthesis translate_off */
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--uniform(seed0,seed1,rand0);
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write(rv0.RandSigned(axiMaster_out.tData'length));
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--write(to_signed(integer(rand0 * 2.0**31),64));
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/* synthesis translate_on */
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write(rand0);
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txFSM<=transmitting;
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end if;
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when transmitting=>
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if writeResponse.trigger then
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/* synthesis translate_off */
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write(rv0.RandSigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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write(rand0);
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write(rand0);
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rand0:=rand0+1;
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rand0:=rand0+1;
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end if;
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/* simulation only. */
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if axiMaster_out.tLast then
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txFSM<=idle;
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end if;
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when others=>null;
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end case;
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end if;
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end process sequencer;
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/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
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process(nReset,irq_write) is
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/* synthesis translate_off */
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/* synthesis translate_off */
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write(rv1.RandUnsigned(axiMaster_out.tData'length));
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variable rv0:RandomPType;
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/* synthesis translate_on */
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/* synthesis translate_on */
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else
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begin
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if not nReset then
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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symbolsPerTransfer<=128x"8";
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elsif rising_edge(irq_write) then
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if axiMaster_out.tLast then
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/* synthesis only. */
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/* synthesis only. */
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/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
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/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
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--symbolsPerTransfer<=(others=>'0');
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--symbolsPerTransfer<=(others=>'0');
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/* Testcase 2: number of symbols per transfer is randomised. */
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/* Testcase 2: number of symbols per transfer is randomised. */
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--uniform(seed0,seed1,rand0);
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--uniform(seed0,seed1,rand0);
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--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
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--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
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--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
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--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
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symbolsPerTransfer<=128x"8";
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/* Truncate symbolsPerTransfer to 8 bits, so that it uses a "small" value for simulation. */
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/* simulation only. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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symbolsPerTransfer<=120x"0" & rv0.RandSigned(64);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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/* synthesis translate_on */
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symbolsPerTransfer<=128x"8";
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end if;
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end if;
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end if;
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end if;
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end process sequencer;
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end process;
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end architecture rtl;
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end architecture rtl;
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