| Line 74... |
Line 74... |
type txStates is (idle,transmitting);
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk,nReset:std_ulogic:='0';
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signal clk,reset:std_ulogic:='0';
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal cnt:unsigned(3 downto 0);
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signal reset:std_ulogic:='0';
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signal testerClk:std_ulogic;
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signal testerClk:std_ulogic;
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--signal trigger:boolean;
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--signal trigger:boolean;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal anlysr_trigger:std_ulogic;
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/* Signal preservations for SignalTap II probing. */
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--attribute keep:boolean;
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--attribute keep of trigger:signal is true;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity work.axiBfmMaster(rtl)
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axiMaster: entity work.axiBfmMaster(rtl)
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port map(
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port map(
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aclk=>irq_write, n_areset=>nReset,
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aclk=>irq_write, n_areset=>not reset,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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| Line 107... |
Line 105... |
outstandingTransactions=>outstandingTransactions,
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outstandingTransactions=>outstandingTransactions,
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dbg_axiTxFSM=>dbg_axiTxFSM
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dbg_axiTxFSM=>dbg_axiTxFSM
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);
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);
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/* Interrupt-request generator. */
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/* Interrupt-request generator. */
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irq_write<=clk when nReset else '0';
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irq_write<=clk when not reset else '0';
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/* Simulation Tester. */
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/* Simulation Tester. */
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/* PLL to generate tester's clock. */
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/* PLL to generate tester's clock. */
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f100MHz: entity altera.pll(syn) port map(
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f100MHz: entity altera.pll(syn) port map(
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areset=>not nReset,
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areset=>'0', --not reset, --not nReset,
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inclk0=>clk,
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inclk0=>clk,
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c0=>testerClk,
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c0=>testerClk,
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locked=>open
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locked=>open
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);
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);
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| Line 130... |
Line 128... |
end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Hardware tester. */
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/* Hardware tester. */
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/*
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por: process(nReset,clk) is
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por: process(reset,clk) is
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--variable cnt:unsigned(7 downto 0):=(others=>'1');
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variable cnt:unsigned(7 downto 0):=x"ff";
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begin
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begin
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if not reset then cnt<=(others=>'1');
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if not nReset then cnt<=(others=>'1');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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nReset<='1';
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reset<='0';
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if cnt>x"8" then nReset<='0'; end if;
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if cnt>0 then reset<='1'; cnt<=cnt-1; end if;
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if cnt>0 then cnt:=cnt-1; end if;
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end if;
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end if;
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end process por;
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end process por;
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*/
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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anlysr_trigger<='1' when writeRequest.trigger else '0';
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anlysr_trigger<='1' when writeRequest.trigger else '0';
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--anlysr_trigger<='1' when reset else '0';
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/* Disable this for synthesis as this is not currently synthesisable.
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/* Disable this for synthesis as this is not currently synthesisable.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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*/
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*/
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/* synthesis translate_off */
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/* synthesis translate_off */
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| Line 160... |
Line 155... |
anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
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anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
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anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
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anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
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--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
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--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
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anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(18)<='1' when clk else '0';
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anlysr_dataIn(18)<='1' when clk else '0';
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anlysr_dataIn(19)<='1' when nReset else '0';
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anlysr_dataIn(19)<='1' when reset else '0';
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anlysr_dataIn(20)<='1' when irq_write else '0';
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anlysr_dataIn(20)<='1' when irq_write else '0';
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anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
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anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
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anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
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anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
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anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
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anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
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anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
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anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
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anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
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anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
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anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
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anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
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anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
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anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
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anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
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anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
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--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
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--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
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anlysr_dataIn(101 downto 98)<=std_logic_vector(cnt);
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anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
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anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
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/* Simulate only if you have compiled Altera's simulation libraries. */
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/* Simulate only if you have compiled Altera's simulation libraries. */
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| Line 249... |
Line 245... |
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/* Data transmitter. */
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/* Data transmitter. */
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sequencer_ns: process(all) is begin
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sequencer_ns: process(all) is begin
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txFSM<=i_txFSM;
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txFSM<=i_txFSM;
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if not nReset then txFSM<=idle;
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if reset then txFSM<=idle;
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else
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else
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case i_txFSM is
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case i_txFSM is
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when idle=>
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when idle=>
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if outstandingTransactions>0 then txFSM<=transmitting; end if;
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if outstandingTransactions>0 then txFSM<=transmitting; end if;
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when transmitting=>
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when transmitting=>
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| Line 264... |
Line 260... |
end case;
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end case;
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end if;
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end if;
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end process sequencer_ns;
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end process sequencer_ns;
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/* Data transmitter. */
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/* Data transmitter. */
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sequencer_op: process(nReset,irq_write) is
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sequencer_op: process(reset,irq_write) is
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/* Local procedures to map BFM signals with the package procedure. */
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/* Local procedures to map BFM signals with the package procedure. */
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procedure read(address:in t_addr) is begin
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procedure read(address:in t_addr) is begin
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read(readRequest,address);
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read(readRequest,address);
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end procedure read;
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end procedure read;
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| Line 285... |
Line 281... |
/* synthesis translate_off */
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/* synthesis translate_off */
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variable rv0:RandomPType;
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variable rv0:RandomPType;
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/* synthesis translate_on */
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/* synthesis translate_on */
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begin
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begin
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if not nReset then
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if reset then
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/* synthesis only. */
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/* synthesis only. */
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rand0:=(others=>'0');
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rand0:=(others=>'0');
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/* simulation only. */
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/* simulation only. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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| Line 318... |
Line 314... |
end if;
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end if;
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end process sequencer_regs;
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end process sequencer_regs;
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/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
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/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
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process(nReset,irq_write) is
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process(reset,irq_write) is
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/* synthesis translate_off */
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/* synthesis translate_off */
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variable rv0:RandomPType;
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variable rv0:RandomPType;
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/* synthesis translate_on */
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/* synthesis translate_on */
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begin
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begin
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if not nReset then
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if reset then
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/* synthesis translate_off */
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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rv0.InitSeed(rv0'instance_name);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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/* synthesis translate_on */
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