| Line 36... |
Line 36... |
*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* TODO remove once generic packages are supported. */
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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library tauhop; use tauhop.fsm.all, tauhop.tlm.all, tauhop.axiTLM.all;
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/* synthesis translate_off */
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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/* synthesis translate_on */
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| Line 84... |
Line 84... |
signal anlysr_trigger:std_ulogic;
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signal anlysr_trigger:std_ulogic;
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|
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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signal selTxn:unsigned(3 downto 0):=4x"0"; -- select PRBS by default.
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signal selTxn:unsigned(3 downto 0):=4x"5"; -- select PRBS by default.
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--signal selTxn:unsigned(3 downto 0):=4x"0";
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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port map(
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port map(
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| Line 115... |
Line 116... |
end process por;
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end process por;
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/* synthesis translate_off */
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/* synthesis translate_off */
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clk<=not clk after clk'period/2;
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clk<=not clk after clk'period/2;
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process is begin
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process is begin
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nReset<='0'; wait for 1 ps;
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nReset<='1'; wait for 1 ps;
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nReset<='1'; wait for 500 ps;
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nReset<='0'; wait for 500 ps;
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nReset<='0';
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nReset<='1';
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Simulation Tester. */
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/* Simulation Tester. */
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