| Line 55... |
Line 55... |
/* Debug ports. */
|
/* Debug ports. */
|
);
|
);
|
end entity user;
|
end entity user;
|
|
|
architecture rtl of user is
|
architecture rtl of user is
|
|
signal reset:std_ulogic:='0';
|
|
signal porCnt:unsigned(3 downto 0);
|
|
signal trigger:boolean;
|
|
|
/* Global counters. */
|
/* Global counters. */
|
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
|
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
|
signal symbolsPerTransfer:i_transactor.t_cnt;
|
signal symbolsPerTransfer:i_transactor.t_cnt;
|
signal outstandingTransactions:i_transactor.t_cnt;
|
signal outstandingTransactions:i_transactor.t_cnt;
|
|
|
| Line 70... |
Line 74... |
signal txFSM,i_txFSM:txStates;
|
signal txFSM,i_txFSM:txStates;
|
|
|
/* Tester signals. */
|
/* Tester signals. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
signal clk,nReset:std_ulogic:='0';
|
signal clk,nReset:std_ulogic:='0';
|
|
attribute period:time; attribute period of clk:signal is 10 ps;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
signal axiMaster_in:t_axi4StreamTransactor_s2m;
|
signal axiMaster_in:t_axi4StreamTransactor_s2m;
|
signal irq_write:std_ulogic; -- clock gating.
|
signal irq_write:std_ulogic; -- clock gating.
|
|
|
|
signal prbs:i_transactor.t_msg;
|
|
|
begin
|
begin
|
/* Bus functional models. */
|
/* Bus functional models. */
|
axiMaster: entity work.axiBfmMaster(rtl)
|
axiMaster: entity tauhop.axiBfmMaster(rtl)
|
|
--axiMaster: entity work.axiBfmMaster(simulation)
|
port map(
|
port map(
|
aclk=>irq_write, n_areset=>nReset,
|
aclk=>irq_write, n_areset=>not reset,
|
|
|
readRequest=>readRequest, writeRequest=>writeRequest,
|
readRequest=>readRequest, writeRequest=>writeRequest,
|
readResponse=>readResponse, writeResponse=>writeResponse,
|
readResponse=>readResponse, writeResponse=>writeResponse,
|
axiMaster_in=>axiMaster_in,
|
axiMaster_in=>axiMaster_in,
|
axiMaster_out=>axiMaster_out,
|
axiMaster_out=>axiMaster_out,
|
| Line 91... |
Line 99... |
symbolsPerTransfer=>symbolsPerTransfer,
|
symbolsPerTransfer=>symbolsPerTransfer,
|
outstandingTransactions=>outstandingTransactions
|
outstandingTransactions=>outstandingTransactions
|
);
|
);
|
|
|
/* Interrupt-request generator. */
|
/* Interrupt-request generator. */
|
irq_write<=clk when nReset else '0';
|
trigger<=txFSM/=i_txFSM or writeResponse.trigger;
|
|
irq_write<=clk when not reset else '0';
|
|
|
/* Simulation Tester. */
|
/* Simulation Tester. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
clk<=not clk after 10 ps;
|
clk<=not clk after clk'period/2;
|
process is begin
|
process is begin
|
nReset<='1'; wait for 1 ps;
|
nReset<='1'; wait for 1 ps;
|
nReset<='0'; wait for 500 ps;
|
nReset<='0'; wait for 500 ps;
|
nReset<='1';
|
nReset<='1';
|
wait;
|
wait;
|
end process;
|
end process;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
|
|
/* Hardware tester. */
|
/* Hardware tester. */
|
|
/* Power-on Reset circuitry. */
|
|
por: process(nReset,clk) is begin
|
|
if not nReset then reset<='1'; porCnt<=(others=>'1');
|
|
elsif rising_edge(clk) then
|
|
reset<='0';
|
|
|
|
if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if;
|
|
end if;
|
|
end process por;
|
|
|
|
/*
|
|
process is
|
|
alias trigger is <<signal axiMaster.trigger:boolean>>;
|
|
alias axiTxState is <<signal axiMaster.next_axiTxState:axiBfmStatesTx>>;
|
|
begin
|
|
-- Remove this assertion once request queue has been implemented.
|
|
if trigger then
|
|
assert axiTxState=idle or axiTxState=payload report "[Error]: Trigger occurs when FSM is not in IDLE or PAYLOAD state." severity error;
|
|
end if;
|
|
wait for clk'period/10;
|
|
end process;
|
|
*/
|
|
|
/* Stimuli sequencer. TODO move to tester/stimuli.
|
/* Stimuli sequencer. TODO move to tester/stimuli.
|
This emulates the AXI4-Stream Slave.
|
This emulates the AXI4-Stream Slave.
|
*/
|
*/
|
/* Simulation-only stimuli sequencer. */
|
/* Simulation-only stimuli sequencer. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
process is begin
|
process is begin
|
|
report "Performing fast read..." severity note;
|
|
|
/* Fast read. */
|
/* Fast read. */
|
while not axiMaster_out.tLast loop
|
while not axiMaster_out.tLast loop
|
/* Wait for tValid to assert. */
|
/* Wait for tValid to assert. */
|
while not axiMaster_out.tValid loop
|
while not axiMaster_out.tValid loop
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
| Line 126... |
Line 159... |
|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
axiMaster_in.tReady<=false;
|
axiMaster_in.tReady<=false;
|
end loop;
|
end loop;
|
|
|
|
report "Completed fast read..." severity note;
|
|
|
|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
|
report "Performing normal read..." severity note;
|
|
|
/* Normal read. */
|
/* Normal read. */
|
while not axiMaster_out.tLast loop
|
while not axiMaster_out.tLast loop
|
/* Wait for tValid to assert. */
|
/* Wait for tValid to assert. */
|
while not axiMaster_out.tValid loop
|
while not axiMaster_out.tValid loop
|
| Line 140... |
Line 177... |
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
axiMaster_in.tReady<=true;
|
axiMaster_in.tReady<=true;
|
|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
axiMaster_in.tReady<=false;
|
axiMaster_in.tReady<=false;
|
|
|
|
wait until falling_edge(clk);
|
|
end loop;
|
|
|
|
report "Completed normal read." severity note;
|
|
|
|
|
|
wait until falling_edge(clk);
|
|
report "Performing slow read..." severity note;
|
|
|
|
/* Slow read. */
|
|
while not axiMaster_out.tLast loop
|
|
/* Wait for tValid to assert. */
|
|
while not axiMaster_out.tValid loop
|
|
wait until falling_edge(clk);
|
|
end loop;
|
|
|
|
wait until falling_edge(clk);
|
|
wait until falling_edge(clk);
|
|
axiMaster_in.tReady<=true;
|
|
|
|
wait until falling_edge(clk);
|
|
axiMaster_in.tReady<=false;
|
|
|
|
wait until falling_edge(clk);
|
end loop;
|
end loop;
|
|
|
|
report "Completed slow read." severity note;
|
|
|
|
|
for i in 0 to 10 loop
|
for i in 0 to 10 loop
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
end loop;
|
end loop;
|
|
report "Performing one-shot read..." severity note;
|
|
|
/* One-shot read. */
|
/* One-shot read. */
|
axiMaster_in.tReady<=true;
|
axiMaster_in.tReady<=true;
|
|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
axiMaster_in.tReady<=false;
|
axiMaster_in.tReady<=false;
|
|
|
|
report "Completed one-shot read." severity note;
|
|
|
wait;
|
wait;
|
end process;
|
end process;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
/* Synthesisable stimuli sequencer. */
|
/* Synthesisable stimuli sequencer. */
|
|
|
|
|
/* Data transmitter. */
|
/* Data transmitter. */
|
|
i_prbs: entity tauhop.prbs31(rtl)
|
|
generic map(
|
|
isParallelLoad=>true,
|
|
tapVector=>(
|
|
/* Example polynomial from Wikipedia:
|
|
http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
|
|
*/
|
|
0|3|31=>true, 1|2|30 downto 4=>false
|
|
)
|
|
)
|
|
port map(
|
|
/* Comment-out for simulation. */
|
|
clk=>irq_write, reset=>reset,
|
|
en=>trigger,
|
|
seed=>32x"ace1", --9x"57",
|
|
prbs=>prbs
|
|
);
|
|
|
sequencer_ns: process(all) is begin
|
sequencer_ns: process(all) is begin
|
txFSM<=i_txFSM;
|
txFSM<=i_txFSM;
|
if not nReset then txFSM<=idle;
|
if reset then txFSM<=idle;
|
else
|
else
|
case i_txFSM is
|
case i_txFSM is
|
when idle=>
|
when idle=>
|
if outstandingTransactions>0 then txFSM<=transmitting; end if;
|
if outstandingTransactions>0 then txFSM<=transmitting; end if;
|
when transmitting=>
|
when transmitting=>
|
| Line 176... |
Line 262... |
when others=> null;
|
when others=> null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process sequencer_ns;
|
end process sequencer_ns;
|
|
|
sequencer_op: process(nReset,irq_write) is
|
sequencer_op: process(reset,irq_write) is
|
/* Local procedures to map BFM signals with the package procedure. */
|
/* Local procedures to map BFM signals with the package procedure. */
|
procedure read(address:in i_transactor.t_addr) is begin
|
procedure read(address:in i_transactor.t_addr) is begin
|
i_transactor.read(readRequest,address);
|
i_transactor.read(readRequest,address);
|
end procedure read;
|
end procedure read;
|
|
|
| Line 197... |
Line 283... |
/* synthesis translate_off */
|
/* synthesis translate_off */
|
variable rv0:RandomPType;
|
variable rv0:RandomPType;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
begin
|
begin
|
if not nReset then
|
-- if reset then
|
/*simulation only. */
|
/*simulation only. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
rv0.InitSeed(rv0'instance_name);
|
-- rv0.InitSeed(rv0'instance_name);
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
elsif falling_edge(irq_write) then
|
-- elsif falling_edge(irq_write) then
|
|
if falling_edge(irq_write) then
|
case txFSM is
|
case txFSM is
|
when transmitting=>
|
when transmitting=>
|
if txFSM/=i_txFSM or writeResponse.trigger then
|
if trigger then
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
write(rv0.RandSigned(axiMaster_out.tData'length));
|
-- write(rv0.RandSigned(axiMaster_out.tData'length));
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
write(prbs);
|
end if;
|
end if;
|
when others=>null;
|
when others=>null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process sequencer_op;
|
end process sequencer_op;
|
| Line 222... |
Line 310... |
i_txFSM<=txFSM;
|
i_txFSM<=txFSM;
|
end if;
|
end if;
|
end process sequencer_regs;
|
end process sequencer_regs;
|
|
|
/* Transaction counter. */
|
/* Transaction counter. */
|
process(nReset,symbolsPerTransfer,irq_write) is begin
|
process(reset,symbolsPerTransfer,irq_write) is begin
|
if not nReset then outstandingTransactions<=symbolsPerTransfer;
|
if reset then outstandingTransactions<=symbolsPerTransfer;
|
elsif falling_edge(irq_write) then
|
elsif rising_edge(irq_write) then
|
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
|
if not axiMaster_out.tLast then
|
if not nReset then outstandingTransactions<=symbolsPerTransfer;
|
|
else
|
|
if outstandingTransactions<1 then
|
if outstandingTransactions<1 then
|
outstandingTransactions<=symbolsPerTransfer;
|
outstandingTransactions<=symbolsPerTransfer;
|
report "No more pending transactions." severity note;
|
report "No more pending transactions." severity note;
|
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
|
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
|
|
if reset then outstandingTransactions<=symbolsPerTransfer; end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
|
process(nReset,irq_write) is
|
process(reset,irq_write) is
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
variable rv0:RandomPType;
|
variable rv0:RandomPType;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
begin
|
begin
|
if not nReset then
|
if reset then
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
rv0.InitSeed(rv0'instance_name);
|
rv0.InitSeed(rv0'instance_name);
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
elsif rising_edge(irq_write) then
|
elsif rising_edge(irq_write) then
|
if axiMaster_out.tLast then
|
if axiMaster_out.tLast then
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
end architecture rtl;
|
end architecture rtl;
|
