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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [user.vhdl] - Diff between revs 17 and 24

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/* synthesis translate_off */
/* synthesis translate_off */
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
/* synthesis translate_on */
/* synthesis translate_on */
 
 
 
--library altera; use altera.stp;
 
 
 
 
entity user is port(
entity user is port(
        /* Comment-out for simulation. */
        /* Comment-out for simulation. */
--      clk,nReset:in std_ulogic;
--      clk,reset:in std_ulogic;
 
 
        /* AXI Master interface */
        /* AXI Master interface */
--      axiMaster_in:in t_axi4StreamTransactor_s2m;
--      axiMaster_in:in t_axi4StreamTransactor_s2m;
        axiMaster_out:buffer t_axi4StreamTransactor_m2s
        axiMaster_out:buffer t_axi4StreamTransactor_m2s;
 
 
        /* Debug ports. */
        /* Debug ports. */
 
        selTxn:in unsigned(3 downto 0):=x"0"
);
);
end entity user;
end entity user;
 
 
architecture rtl of user is
architecture rtl of user is
        signal reset:std_ulogic:='0';
        signal i_reset:std_ulogic:='0';
        signal porCnt:unsigned(3 downto 0);
        signal porCnt:unsigned(3 downto 0);
        signal trigger:boolean;
 
 
 
        /* Global counters. */
        /* Global counters. */
        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
        signal symbolsPerTransfer:i_transactor.t_cnt;
        signal symbolsPerTransfer:i_transactor.t_cnt;
        signal outstandingTransactions:i_transactor.t_cnt;
        signal outstandingTransactions:i_transactor.t_cnt;
 
 
        /* BFM signalling. */
        /* BFM signalling. */
        signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
        signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
        signal readResponse,writeResponse:i_transactor.t_bfm;
        signal readResponse,writeResponse:i_transactor.t_bfm;
 
 
        type txStates is (idle,transmitting);
 
        signal txFSM,i_txFSM:txStates;
 
 
 
        /* Tester signals. */
        /* Tester signals. */
        /* synthesis translate_off */
        /* synthesis translate_off */
        signal clk,nReset:std_ulogic:='0';
        signal clk,reset:std_ulogic:='0';
        attribute period:time; attribute period of clk:signal is 10 ps;
        attribute period:time; attribute period of clk:signal is 10 ps;
        /* synthesis translate_on */
        /* synthesis translate_on */
 
 
 
        signal dbg_axiTxFSM:axiBfmStatesTx;
 
        signal anlysr_dataIn:std_logic_vector(255 downto 0);
 
        signal anlysr_trigger:std_ulogic;
 
 
        signal axiMaster_in:t_axi4StreamTransactor_s2m;
        signal axiMaster_in:t_axi4StreamTransactor_s2m;
        signal irq_write:std_ulogic;            -- clock gating.
        signal irq_write:std_ulogic;            -- clock gating.
 
 
        signal prbs:i_transactor.t_msg;
 
 
 
begin
begin
        /* Bus functional models. */
        /* Bus functional models. */
        axiMaster: entity tauhop.axiBfmMaster(rtl)
        axiMaster: entity tauhop.axiBfmMaster(rtl)
        --axiMaster: entity work.axiBfmMaster(simulation)
 
                port map(
                port map(
                        aclk=>irq_write, n_areset=>not reset,
                        aclk=>irq_write, n_areset=>not i_reset,
 
 
                        readRequest=>readRequest,       writeRequest=>writeRequest,
                        readRequest=>readRequest,       writeRequest=>writeRequest,
                        readResponse=>readResponse,     writeResponse=>writeResponse,
                        readResponse=>readResponse,     writeResponse=>writeResponse,
                        axiMaster_in=>axiMaster_in,
                        axiMaster_in=>axiMaster_in,
                        axiMaster_out=>axiMaster_out,
                        axiMaster_out=>axiMaster_out,
 
 
                        symbolsPerTransfer=>symbolsPerTransfer,
                        symbolsPerTransfer=>symbolsPerTransfer,
                        outstandingTransactions=>outstandingTransactions
                        outstandingTransactions=>outstandingTransactions,
 
                        dbg_axiTxFSM=>dbg_axiTxFSM
        );
        );
 
 
        /* Interrupt-request generator. */
        /* Clocks and reset. */
        trigger<=txFSM/=i_txFSM or writeResponse.trigger;
 
        irq_write<=clk when not reset else '0';
 
 
 
        /* Simulation Tester. */
 
        /* synthesis translate_off */
 
        clk<=not clk after clk'period/2;
 
        process is begin
 
                nReset<='1'; wait for 1 ps;
 
                nReset<='0'; wait for 500 ps;
 
                nReset<='1';
 
                wait;
 
        end process;
 
        /* synthesis translate_on */
 
 
 
 
 
        /* Hardware tester. */
 
        /* Power-on Reset circuitry. */
        /* Power-on Reset circuitry. */
        por: process(nReset,clk) is begin
        por: process(reset,clk) is begin
                if not nReset then reset<='1'; porCnt<=(others=>'1');
                if reset then i_reset<='1'; porCnt<=(others=>'1');
                elsif rising_edge(clk) then
                elsif rising_edge(clk) then
                        reset<='0';
                        i_reset<='0';
 
 
                        if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if;
                        if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if;
                end if;
                end if;
        end process por;
        end process por;
 
 
/*
 
        process is
 
                alias trigger is <<signal axiMaster.trigger:boolean>>;
 
                alias axiTxState is <<signal axiMaster.next_axiTxState:axiBfmStatesTx>>;
 
        begin
 
                -- Remove this assertion once request queue has been implemented.
 
                if trigger then
 
                        assert axiTxState=idle or axiTxState=payload report "[Error]: Trigger occurs when FSM is not in IDLE or PAYLOAD state." severity error;
 
                end if;
 
                wait for clk'period/10;
 
        end process;
 
*/
 
 
 
        /* Stimuli sequencer. TODO move to tester/stimuli.
 
                This emulates the AXI4-Stream Slave.
 
        */
 
        /* Simulation-only stimuli sequencer. */
 
        /* synthesis translate_off */
        /* synthesis translate_off */
 
        clk<=not clk after clk'period/2;
        process is begin
        process is begin
                report "Performing fast read..." severity note;
                reset<='0'; wait for 1 ps;
 
                reset<='1'; wait for 500 ps;
                /* Fast read. */
                reset<='0';
                while not axiMaster_out.tLast loop
 
                        /* Wait for tValid to assert. */
 
                        while not axiMaster_out.tValid loop
 
                                wait until falling_edge(clk);
 
                        end loop;
 
 
 
                        axiMaster_in.tReady<=true;
 
 
 
                        wait until falling_edge(clk);
 
                        axiMaster_in.tReady<=false;
 
                end loop;
 
 
 
                report "Completed fast read..." severity note;
 
 
 
 
 
                wait until falling_edge(clk);
 
                report "Performing normal read..." severity note;
 
 
 
                /* Normal read. */
 
                while not axiMaster_out.tLast loop
 
                        /* Wait for tValid to assert. */
 
                        while not axiMaster_out.tValid loop
 
                                wait until falling_edge(clk);
 
                        end loop;
 
 
 
                        wait until falling_edge(clk);
 
                        axiMaster_in.tReady<=true;
 
 
 
                        wait until falling_edge(clk);
 
                        axiMaster_in.tReady<=false;
 
 
 
                        wait until falling_edge(clk);
 
                end loop;
 
 
 
                report "Completed normal read." severity note;
 
 
 
 
 
                wait until falling_edge(clk);
 
                report "Performing slow read..." severity note;
 
 
 
                /* Slow read. */
 
                while not axiMaster_out.tLast loop
 
                        /* Wait for tValid to assert. */
 
                        while not axiMaster_out.tValid loop
 
                                wait until falling_edge(clk);
 
                        end loop;
 
 
 
                        wait until falling_edge(clk);
 
                        wait until falling_edge(clk);
 
                        axiMaster_in.tReady<=true;
 
 
 
                        wait until falling_edge(clk);
 
                        axiMaster_in.tReady<=false;
 
 
 
                        wait until falling_edge(clk);
 
                end loop;
 
 
 
                report "Completed slow read." severity note;
 
 
 
 
 
                for i in 0 to 10 loop
 
                        wait until falling_edge(clk);
 
                end loop;
 
                report "Performing one-shot read..." severity note;
 
 
 
                /* One-shot read. */
 
                axiMaster_in.tReady<=true;
 
 
 
                wait until falling_edge(clk);
 
                axiMaster_in.tReady<=false;
 
 
 
                report "Completed one-shot read." severity note;
 
 
 
                wait;
                wait;
        end process;
        end process;
        /* synthesis translate_on */
        /* synthesis translate_on */
 
 
        /* Synthesisable stimuli sequencer. */
        /* Simulation Tester. */
 
 
 
 
        /* Data transmitter. */
        /* Hardware tester. */
        i_prbs: entity tauhop.prbs31(rtl)
        bist: entity work.tester(rtl) port map(
                generic map(
                clk=>clk, reset=>i_reset,
                        isParallelLoad=>true,
                axiMaster_in=>axiMaster_in,
                        tapVector=>(
                axiMaster_out=>axiMaster_out,
                                /* Example polynomial from Wikipedia:
                readRequest=>readRequest, writeRequest=>writeRequest,
                                        http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
                readResponse=>readResponse, writeResponse=>writeResponse,
                                */
                irq_write=>irq_write,
                                0|3|31=>true, 1|2|30 downto 4=>false
                symbolsPerTransfer=>symbolsPerTransfer,
                        )
                outstandingTransactions=>outstandingTransactions,
                )
                selTxn=>selTxn
                port map(
 
                        /* Comment-out for simulation. */
 
                        clk=>irq_write, reset=>reset,
 
                        en=>trigger,
 
                        seed=>32x"ace1",        --9x"57",
 
                        prbs=>prbs
 
                );
                );
 
 
        sequencer_ns: process(all) is begin
 
                txFSM<=i_txFSM;
 
                if reset then txFSM<=idle;
 
                else
 
                        case i_txFSM is
 
                                when idle=>
 
                                        if outstandingTransactions>0 then txFSM<=transmitting; end if;
 
                                when transmitting=>
 
                                        if axiMaster_out.tLast then
 
                                                txFSM<=idle;
 
                                        end if;
 
                                when others=> null;
 
                        end case;
 
                end if;
 
        end process sequencer_ns;
 
 
 
        sequencer_op: process(reset,irq_write) is
 
                /* Local procedures to map BFM signals with the package procedure. */
 
                procedure read(address:in i_transactor.t_addr) is begin
 
                        i_transactor.read(readRequest,address);
 
                end procedure read;
 
 
 
                procedure write(data:in i_transactor.t_msg) is begin
 
                        i_transactor.write(request=>writeRequest, address=>(others=>'-'), data=>data);
 
                end procedure write;
 
 
 
                variable isPktError:boolean;
 
 
 
                /* Tester variables. */
 
                /* Synthesis-only randomisation. */
 
 
 
                /* Simulation-only randomisation. */
 
                /* synthesis translate_off */
 
                variable rv0:RandomPType;
 
                /* synthesis translate_on */
 
 
 
        begin
 
--              if reset then
 
                        /* simulation only. */
 
                        /* synthesis translate_off */
 
--                      rv0.InitSeed(rv0'instance_name);
 
                        /* synthesis translate_on */
 
--              elsif falling_edge(irq_write) then
 
                if falling_edge(irq_write) then
 
                        case txFSM is
 
                                when transmitting=>
 
                                        if trigger then
 
                                                /* synthesis translate_off */
 
--                                              write(rv0.RandSigned(axiMaster_out.tData'length));
 
                                                /* synthesis translate_on */
 
                                                write(prbs);
 
                                        end if;
 
                                when others=>null;
 
                        end case;
 
                end if;
 
        end process sequencer_op;
 
 
 
        sequencer_regs: process(irq_write) is begin
 
                if falling_edge(irq_write) then
 
                        i_txFSM<=txFSM;
 
                end if;
 
        end process sequencer_regs;
 
 
 
        /* Transaction counter. */
 
        process(reset,symbolsPerTransfer,irq_write) is begin
 
                if reset then outstandingTransactions<=symbolsPerTransfer;
 
                elsif rising_edge(irq_write) then
 
                        if not axiMaster_out.tLast then
 
                                if outstandingTransactions<1 then
 
                                        outstandingTransactions<=symbolsPerTransfer;
 
                                        report "No more pending transactions." severity note;
 
                                elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
 
                                end if;
 
                        end if;
 
 
 
                        /* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
 
                        if reset then outstandingTransactions<=symbolsPerTransfer; end if;
 
                end if;
 
        end process;
 
 
 
        /* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
 
        process(reset,irq_write) is
 
                /* synthesis translate_off */
 
                variable rv0:RandomPType;
 
                /* synthesis translate_on */
 
        begin
 
                if reset then
 
                        /* synthesis translate_off */
 
                        rv0.InitSeed(rv0'instance_name);
 
                        symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
 
                        report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
 
                        /* synthesis translate_on */
 
                elsif rising_edge(irq_write) then
 
                        if axiMaster_out.tLast then
 
                                /* synthesis translate_off */
 
                                symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
 
                                report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
 
                                /* synthesis translate_on */
 
                        end if;
 
                end if;
 
        end process;
 
end architecture rtl;
end architecture rtl;
 
 
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