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//---------------------------------------------------------------------------
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// Binary to BCD converter, serial implementation, 1 clock per input bit.
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//
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//
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// Description: See description below (which suffices for IP core
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// specification document.)
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//
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// Copyright (C) 2002 John Clayton and OPENCORES.ORG (this Verilog version)
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source.
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// If not, download it from http://www.opencores.org/lgpl.shtml
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//
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//-----------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date : Nov. 19, 2003
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// Update: Nov. 19, 2003 Copied this file from "led_display_driver.v" and
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// modified it.
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// Update: Nov. 24, 2003 Fixed bcd_asl function, tested module. It works!
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// Update: Nov. 25, 2003 Changed bit_counter and related logic so that long
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// start pulses produce correct results at the end of
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// the pulse.
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//
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//-----------------------------------------------------------------------------
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// Description:
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//
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// This module takes a binary input, and converts it into BCD output, with each
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// binary coded decimal digit of course occupying 4-bits.
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// The user can specify the number of input bits separately from the number of
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// output digits. Be sure that you have specified enough output digits to
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// represent the largest number you expect on the binary input, or else the
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// most significant digits of the result will be cut off.
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//
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//-----------------------------------------------------------------------------
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module binary_to_bcd (
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clk_i,
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ce_i,
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rst_i,
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start_i,
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dat_binary_i,
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dat_bcd_o,
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done_o
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);
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parameter BITS_IN_PP = 16; // # of bits of binary input
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parameter BCD_DIGITS_OUT_PP = 5; // # of digits of BCD output
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parameter BIT_COUNT_WIDTH_PP = 4; // Width of bit counter
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// I/O declarations
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input clk_i; // clock signal
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input ce_i; // clock enable input
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input rst_i; // synchronous reset
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input start_i; // initiates a conversion
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input [BITS_IN_PP-1:0] dat_binary_i; // input bus
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output [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o; // output bus
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output done_o; // indicates conversion is done
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reg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;
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// Internal signal declarations
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reg [BITS_IN_PP-1:0] bin_reg;
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reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;
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wire [BITS_IN_PP-1:0] bin_next;
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reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;
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reg busy_bit;
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reg [BIT_COUNT_WIDTH_PP-1:0] bit_count;
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wire bit_count_done;
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//--------------------------------------------------------------------------
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// Functions & Tasks
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//--------------------------------------------------------------------------
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function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;
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input [4*BCD_DIGITS_OUT_PP-1:0] din;
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input newbit;
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integer k;
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reg cin;
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reg [3:0] digit;
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reg [3:0] digit_less;
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begin
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cin = newbit;
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for (k=0; k<BCD_DIGITS_OUT_PP; k=k+1)
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begin
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digit[3] = din[4*k+3];
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digit[2] = din[4*k+2];
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digit[1] = din[4*k+1];
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digit[0] = din[4*k];
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digit_less = digit - 5;
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if (digit > 4'b0100)
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begin
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bcd_asl[4*k+3] = digit_less[2];
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bcd_asl[4*k+2] = digit_less[1];
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bcd_asl[4*k+1] = digit_less[0];
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bcd_asl[4*k+0] = cin;
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cin = 1'b1;
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end
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else
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begin
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bcd_asl[4*k+3] = digit[2];
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bcd_asl[4*k+2] = digit[1];
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bcd_asl[4*k+1] = digit[0];
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bcd_asl[4*k+0] = cin;
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cin = 1'b0;
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end
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end // end of for loop
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end
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endfunction
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//--------------------------------------------------------------------------
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// Module code
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//--------------------------------------------------------------------------
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// Perform proper shifting, binary ASL and BCD ASL
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assign bin_next = {bin_reg,1'b0};
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always @(bcd_reg or bin_reg)
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begin
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bcd_next <= bcd_asl(bcd_reg,bin_reg[BITS_IN_PP-1]);
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end
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// Busy bit, input and output registers
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always @(posedge clk_i)
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begin
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if (rst_i)
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begin
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busy_bit <= 0; // Synchronous reset
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dat_bcd_o <= 0;
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end
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else if (start_i && ~busy_bit)
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begin
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busy_bit <= 1;
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bin_reg <= dat_binary_i;
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bcd_reg <= 0;
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end
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else if (busy_bit && ce_i && bit_count_done && ~start_i)
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begin
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busy_bit <= 0;
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dat_bcd_o <= bcd_next;
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end
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else if (busy_bit && ce_i && ~bit_count_done)
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begin
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bcd_reg <= bcd_next;
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bin_reg <= bin_next;
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end
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end
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assign done_o = ~busy_bit;
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// Bit counter
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always @(posedge clk_i)
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begin
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if (~busy_bit) bit_count <= 0;
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else if (ce_i && ~bit_count_done) bit_count <= bit_count + 1;
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end
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assign bit_count_done = (bit_count == (BITS_IN_PP-1));
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endmodule
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