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[/] [brisc/] [trunk/] [register_e.v] - Diff between revs 2 and 3
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module register_e(in, out, clk, reset_n, enable);
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parameter dw = 8 ;
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input [dw-1:0] in;
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input clk;
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input reset_n;
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input enable;
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output reg [dw-1:0] out;
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always @(posedge clk or negedge reset_n)
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begin
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if (!reset_n)
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out <= 0;
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else if (enable)
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out <= in;
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// else
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// out <= {dw{1'bx}};
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end
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endmodule
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