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-------------------------------------------------------------------
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-- --
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-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- This source file is free software; you can redistribute it --
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-- and/or modify it under the terms of the GNU Lesser General --
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-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
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-- --
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-- This source is distributed in the hope that it will be --
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-- useful, but WITHOUT ANY WARRANTY; without even the implied --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- details. --
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-- --
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-- You should have received a copy of the GNU Lesser General --
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-- Public License along with this source; if not, download it --
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-- from http://www.opencores.org/lgpl.shtml --
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-- --
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-------------------------------------------------------------------
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library hotan;
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library hotan;
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use hotan.sha_256_pkg.all;
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use hotan.sha_256_pkg.all;
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library ieee;
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library ieee;
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use ieee.NUMERIC_STD.all;
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use ieee.NUMERIC_STD.all;
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use ieee.STD_LOGIC_UNSIGNED.all;
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use ieee.STD_LOGIC_UNSIGNED.all;
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| Line 24... |
Line 52... |
iClkProcess : in STD_LOGIC;
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iClkProcess : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iValid_p : in STD_LOGIC;
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iValid_p : in STD_LOGIC;
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ivAddr : in STD_LOGIC_VECTOR(3 downto 0);
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ivAddr : in STD_LOGIC_VECTOR(3 downto 0);
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ivData : in STD_LOGIC_VECTOR(31 downto 0);
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ivData : in STD_LOGIC_VECTOR(31 downto 0);
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oReachEnd : out STD_LOGIC;
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oReachEnd_p : out STD_LOGIC;
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oFoundNonce : out STD_LOGIC;
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oFoundNonce_p : out STD_LOGIC;
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ovNonce : out STD_LOGIC_VECTOR(31 downto 0);
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ovNonce : out STD_LOGIC_VECTOR(31 downto 0);
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ovDigest : out tDwordArray(0 to 7) );
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ovDigest : out tDwordArray(0 to 7) );
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end component;
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end component;
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component sha_256_chunk
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component sha_256_chunk
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generic(
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generic(
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gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
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gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
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gBASE_DELAY : integer := 1
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gBASE_DELAY : integer := 3;
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gOUT_VALID_GEN : boolean := false;
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gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
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);
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);
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port(
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port(
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iClk : in STD_LOGIC;
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iClk : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iValid : in STD_LOGIC;
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iValid : in STD_LOGIC;
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Line 86... |
ovH2 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH2 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH3 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH3 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH4 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH4 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH5 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH5 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH6 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH6 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH7 : out STD_LOGIC_VECTOR(31 downto 0) );
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ovH7 : out STD_LOGIC_VECTOR(31 downto 0);
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oValid : out std_logic);
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end component;
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end component;
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component pipelines_without_reset IS
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component pipelines_without_reset IS
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GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
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GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
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PORT(
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PORT(
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Line 109... |
signal iRst_async : STD_LOGIC := '1';
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signal iRst_async : STD_LOGIC := '1';
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signal iValid_p : STD_LOGIC := '0';
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signal iValid_p : STD_LOGIC := '0';
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signal ivAddr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
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signal ivAddr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
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signal ivData : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivData : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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-- Observed signals - signals mapped to the output ports of tested entity
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-- Observed signals - signals mapped to the output ports of tested entity
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signal oReachEnd : STD_LOGIC := '0';
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signal oReachEnd_p : STD_LOGIC := '0';
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signal oFoundNonce : STD_LOGIC := '0';
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signal oFoundNonce_p : STD_LOGIC := '0';
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signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0'));
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-- Add your code here ...
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-- Add your code here ...
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constant cREG_CLK_PERIOD : time := 30 ns; -- 33M Register Clock
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constant cPROC_CLK_PERIOD : time := 10 ns; -- 100M Processing Clock
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constant cRESET_INTERVAL : time := 71 ns;
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constant cSTRAT_TEST : integer := 25;
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constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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constant cCMD_IDLE : std_logic_vector(15 downto 0) := X"0000";
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constant cCMD_NOP : std_logic_vector(15 downto 0) := X"0000";
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constant cCMD_RESET : std_logic_vector(15 downto 0) := X"CAFE";
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constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
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constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
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signal svWork : tDwordArray(0 to 31) := (others=>(others=>'0'));
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signal svWork : tDwordArray(0 to 31) := (others=>(others=>'0'));
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signal siWriteCnt : std_logic_vector(31 downto 0) := (others => '0');
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signal svWriteCnt : std_logic_vector(31 downto 0) := (others => '0');
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signal sHashMidStateValidIn : std_logic := '0';
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signal sHashMidStateValidIn : std_logic := '0';
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signal sHashMidStateValidOut : std_logic := '0';
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signal sHashMidStateValidOut : std_logic := '0';
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signal svHashMidStateDataOut : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal svHashMidStateDataOut : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal svMidState : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal svMidState : tDwordArray(0 to 7) := (others=>(others=>'0'));
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Line 149... |
iClkProcess => iClkProcess,
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iClkProcess => iClkProcess,
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iRst_async => iRst_async,
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iRst_async => iRst_async,
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iValid_p => iValid_p,
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iValid_p => iValid_p,
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ivAddr => ivAddr,
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ivAddr => ivAddr,
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ivData => ivData,
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ivData => ivData,
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oReachEnd => oReachEnd,
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oReachEnd_p => oReachEnd_p,
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oFoundNonce => oFoundNonce,
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oFoundNonce_p => oFoundNonce_p,
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ovNonce => ovNonce,
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ovNonce => ovNonce,
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ovDigest => ovDigest
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ovDigest => ovDigest
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);
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);
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-- Add your stimulus here ...
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-- Add your stimulus here ...
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iClkReg <= not iClkReg after 5 ns;
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iClkReg <= not iClkReg after (cREG_CLK_PERIOD / 2);
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iClkProcess <= not iClkProcess after 5 ns;
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iClkProcess <= not iClkProcess after (cPROC_CLK_PERIOD / 2);
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iRst_async <= '0' after 71 ns;
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iRst_async <= '0' after cRESET_INTERVAL;
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svWork(0) <= X"02000000" after 251 ns;
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-- This test vector is derive from block 266243, notice the endianess changment of converting JSON data to test vector
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svWork(1) <= X"ea144059" after 251 ns;
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-- blockId: 266243
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svWork(2) <= X"2a8b0d36" after 251 ns;
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-- blockHash: 000000000000000399572203a6035acb2d68944c9c047435a5e9f11d40daa4ee
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svWork(3) <= X"b2e5f8a4" after 251 ns;
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-- merkleroot: 0e4cdeacdeaee092dcbb702887e323a036f6bd60d003448e965528adb5ffdf11
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svWork(4) <= X"85db1c04" after 251 ns;
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-- nonce: 3064385291
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svWork(5) <= X"ca9290ca" after 251 ns;
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-- previousblockhash: 0000000000000005f2c7bd05ca9092ca041cdb85a4f8e5b2360d8b2a594014ea
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svWork(6) <= X"05bdc7f2" after 251 ns;
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-- hash: 000000000000000399572203a6035acb2d68944c9c047435a5e9f11d40daa4ee
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svWork(7) <= X"05000000" after 251 ns;
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-- version: 2
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svWork(8) <= X"00000000" after 251 ns;
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-- height: 266243
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svWork(9) <= X"11dfffb5" after 251 ns;
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-- difficulty: 390928787.63808584
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svWork(10) <= X"ad285596" after 251 ns;
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-- confirmations: 1
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svWork(11) <= X"8e4403d0" after 251 ns;
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-- time: 1382820355
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svWork(12) <= X"60bdf636" after 251 ns;
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-- bits: 190afc85
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svWork(13) <= X"a023e387" after 251 ns;
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-- size: 227682
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svWork(14) <= X"2870bbdc" after 251 ns;
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svWork(0) <= X"02000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(15) <= X"92e0aede" after 251 ns;
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svWork(1) <= X"ea144059" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(16) <= X"acde4c0e" after 251 ns;
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svWork(2) <= X"2a8b0d36" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(17) <= X"032A6C52" after 251 ns;
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svWork(3) <= X"b2e5f8a4" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(18) <= X"85fc0a19" after 251 ns;
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svWork(4) <= X"85db1c04" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(19) <= X"0BCFA6B6" after 251 ns;
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svWork(5) <= X"ca9290ca" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(6) <= X"05bdc7f2" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(7) <= X"05000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(8) <= X"00000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(9) <= X"11dfffb5" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(10) <= X"ad285596" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(11) <= X"8e4403d0" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(12) <= X"60bdf636" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(13) <= X"a023e387" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(14) <= X"2870bbdc" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(15) <= X"92e0aede" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(16) <= X"acde4c0e" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(17) <= X"032A6C52" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(18) <= X"85fc0a19" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(19) <= X"0BCFA6B6" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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process(iClkReg, iRst_async)
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process(iClkReg, iRst_async)
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begin
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begin
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if iRst_async = '1' then
|
if iRst_async = '1' then
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siWriteCnt <= (others => '0');
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svWriteCnt <= (others => '0');
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iValid_p <= '0';
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iValid_p <= '0';
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elsif rising_edge(iClkReg) then
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elsif rising_edge(iClkReg) then
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if sMidStateValid = '1' then
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if sMidStateValid = '1' then
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siWriteCnt <= siWriteCnt + '1';
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svWriteCnt <= svWriteCnt + '1';
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end if;
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end if;
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|
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if siWriteCnt(3 downto 0) = X"F" and siWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then
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if svWriteCnt(3 downto 0) = X"F" and svWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then
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iValid_p <= '1';
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iValid_p <= '1';
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else
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else
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iValid_p <= '0';
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iValid_p <= '0';
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end if;
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end if;
|
end if;
|
end if;
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| Line 172... |
Line 222... |
begin
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begin
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if iRst_async = '1' then
|
if iRst_async = '1' then
|
ivAddr <= (others=>'0');
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ivAddr <= (others=>'0');
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ivData <= (others=>'0');
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ivData <= (others=>'0');
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elsif rising_edge(iClkReg) then
|
elsif rising_edge(iClkReg) then
|
if siWriteCnt(3 downto 0) = X"F" then
|
if svWriteCnt(3 downto 0) = X"F" then
|
case siWriteCnt(15 downto 4) is
|
case svWriteCnt(15 downto 4) is
|
when X"000" =>
|
when X"000" =>
|
ivAddr <= X"0";
|
ivAddr <= X"0";
|
ivData <= svMidState(0);
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ivData <= svMidState(0);
|
|
|
when X"001" =>
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when X"001" =>
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| Line 224... |
Line 274... |
ivAddr <= X"B";
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ivAddr <= X"B";
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ivData <= svWork(19) - X"20";
|
ivData <= svWork(19) - X"20";
|
|
|
when X"00C" =>
|
when X"00C" =>
|
ivAddr <= X"C";
|
ivAddr <= X"C";
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ivData <= svWork(19); -- + X"02";
|
ivData <= svWork(19) + X"20";
|
|
|
when X"00D" =>
|
when X"00D" =>
|
ivAddr <= cCMD_ADDR;
|
ivAddr <= cCMD_ADDR;
|
ivData <= X"0000" & cCMD_START;
|
ivData <= X"0000" & cCMD_START;
|
|
|
when others =>
|
when others =>
|
ivAddr <= cCMD_ADDR;
|
ivAddr <= cCMD_ADDR;
|
ivData <= X"0000" & cCMD_IDLE;
|
ivData <= X"0000" & cCMD_NOP;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
sHashMidStateValidIn <= '1' after 251 ns, '0' after 261 ns;
|
sHashMidStateValidIn <= '1' after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns), '0' after (cSTRAT_TEST * cPROC_CLK_PERIOD + cPROC_CLK_PERIOD + 1 ns);
|
|
|
sha_256_chunk_inst_HashMidState : sha_256_chunk
|
sha_256_chunk_inst_HashMidState : sha_256_chunk
|
generic map(
|
generic map(
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gMSG_IS_CONSTANT => (others=>'0'),
|
gMSG_IS_CONSTANT => (others=>'0'),
|
gH_IS_CONST => (others=>'1'),
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gH_IS_CONST => (others=>'1'),
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gBASE_DELAY => gBASE_DELAY
|
gBASE_DELAY => gBASE_DELAY,
|
|
gOUT_VALID_GEN => true
|
)
|
)
|
port map (
|
port map (
|
iClk => iClkProcess,
|
iClk => iClkProcess,
|
iRst_async => iRst_async,
|
iRst_async => iRst_async,
|
iValid => sHashMidStateValidIn,
|
iValid => sHashMidStateValidIn,
|
| Line 270... |
Line 321... |
ovH2 => svHashMidStateDataOut(2),
|
ovH2 => svHashMidStateDataOut(2),
|
ovH3 => svHashMidStateDataOut(3),
|
ovH3 => svHashMidStateDataOut(3),
|
ovH4 => svHashMidStateDataOut(4),
|
ovH4 => svHashMidStateDataOut(4),
|
ovH5 => svHashMidStateDataOut(5),
|
ovH5 => svHashMidStateDataOut(5),
|
ovH6 => svHashMidStateDataOut(6),
|
ovH6 => svHashMidStateDataOut(6),
|
ovH7 => svHashMidStateDataOut(7)
|
ovH7 => svHashMidStateDataOut(7),
|
);
|
|
|
|
pipelines_without_reset_Valid : pipelines_without_reset
|
oValid => sHashMidStateValidOut
|
GENERIC map(gBUS_WIDTH => 1, gNB_PIPELINES => (64 * gBASE_DELAY + 1))
|
|
PORT map(
|
|
iClk => iClkProcess,
|
|
iInput => sHashMidStateValidIn,
|
|
ivInput => (others=>'0'),
|
|
oDelayed_output => sHashMidStateValidOut,
|
|
ovDelayed_output => open
|
|
);
|
);
|
|
|
|
-- pipelines_without_reset_Valid : pipelines_without_reset
|
|
-- GENERIC map(gBUS_WIDTH => 1, gNB_PIPELINES => (64 * gBASE_DELAY + 1))
|
|
-- PORT map(
|
|
-- iClk => iClkProcess,
|
|
-- iInput => sHashMidStateValidIn,
|
|
-- ivInput => (others=>'0'),
|
|
-- oDelayed_output => sHashMidStateValidOut,
|
|
-- ovDelayed_output => open
|
|
-- );
|
|
|
process(iClkProcess)
|
process(iClkProcess)
|
begin
|
begin
|
if rising_edge(iClkProcess) then
|
if rising_edge(iClkProcess) then
|
if sHashMidStateValidOut = '1' then
|
if sHashMidStateValidOut = '1' then
|
svMidState <= svHashMidStateDataOut;
|
svMidState <= svHashMidStateDataOut;
|
