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-- Copyright (c) 2013 VariStream
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-------------------------------------------------------------------
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-- Auther : Yu Peng
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-- --
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-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- This source file is free software; you can redistribute it --
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-- and/or modify it under the terms of the GNU Lesser General --
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-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
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-- --
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-- This source is distributed in the hope that it will be --
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-- useful, but WITHOUT ANY WARRANTY; without even the implied --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- details. --
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-- --
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-- You should have received a copy of the GNU Lesser General --
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-- Public License along with this source; if not, download it --
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-- from http://www.opencores.org/lgpl.shtml --
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-- --
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-------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity btc_dsha is
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entity btc_dsha is
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generic(
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generic(
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gBASE_DELAY : integer := 1
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gBASE_DELAY : integer := 1
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);
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);
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port(
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port(
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iRst_async : in std_logic := '0';
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iClkReg : in std_logic := '0';
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iClkReg : in std_logic := '0';
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iClkProcess : in std_logic := '0';
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iClkProcess : in std_logic := '0';
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iRst_async : in std_logic := '0';
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iValid_p : in std_logic := '0';
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iValid_p : in std_logic := '0';
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ivAddr : in std_logic_vector(3 downto 0) := (others=>'0');
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ivAddr : in std_logic_vector(3 downto 0) := (others=>'0');
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ivData : in std_logic_vector(31 downto 0) := (others=>'0');
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ivData : in std_logic_vector(31 downto 0) := (others=>'0');
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oSyncReset : out std_logic -- Synchronous reset output
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oSyncReset : out std_logic -- Synchronous reset output
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);
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);
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end component;
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end component;
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constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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constant cCMD_IDLE : std_logic_vector(15 downto 0) := X"0000";
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constant cCMD_RESET : std_logic_vector(15 downto 0) := X"CAFE";
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constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
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constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
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constant cPROCESS_DEALY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1, 16);
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constant cPROCESS_DEALY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1, 16);
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constant cCMP_DELAY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1 + 2, 16);
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constant cCMP_DELAY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1 + 2, 16);
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signal svStartNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svStartNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svEndNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svEndNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svCmd : std_logic_vector(15 downto 0) := (others=>'0');
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signal svCmd : std_logic_vector(15 downto 0) := (others=>'0');
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signal sCmdValid_syncReg_p : std_logic := '0';
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signal sCmdValid_syncReg_p : std_logic := '0';
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signal sCmdReset : std_logic := '0';
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signal sCmdStart_syncReg_p : std_logic := '0';
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signal sCmdStart_syncReg_p : std_logic := '0';
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signal sCmdStart_syncProcess_p : std_logic := '0';
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signal sCmdStart_syncProcess_p : std_logic := '0';
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signal sCmdStart_syncProcess_p_1d : std_logic := '0';
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signal sCmdStart_syncProcess_p_1d : std_logic := '0';
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signal sProcess : tProcessStateMachine := stIdle;
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signal sProcess : tProcessStateMachine := stIdle;
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signal sCmpResultValid : std_logic := '0';
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signal sCmpResultValid : std_logic := '0';
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signal sFoundNonceToIdle : std_logic := '0';
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signal sFoundNonceToIdle : std_logic := '0';
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signal sReachEndToIdle : std_logic := '0';
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signal sReachEndToIdle : std_logic := '0';
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begin
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begin
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SyncReset_inst_Process : SyncReset
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SyncReset_inst_Process : SyncReset
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port map(
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port map(
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iClk => iClkProcess,
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iClk => iClkProcess,
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iAsyncReset => iRst_async,
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iAsyncReset => iRst_async,
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oSyncReset => sReset_syncProcess
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oSyncReset => sReset_syncProcess
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end process;
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end process;
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process(iClkReg, iRst_async)
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process(iClkReg, iRst_async)
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begin
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begin
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if iRst_async = '1' then
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if iRst_async = '1' then
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sCmdReset <= '0';
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sCmdValid_syncReg_p <= '0';
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sCmdValid_syncReg_p <= '0';
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sCmdStart_syncReg_p <= '0';
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elsif rising_edge(iClkReg) then
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elsif rising_edge(iClkReg) then
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if iValid_p = '1' and ivAddr = cCMD_ADDR then
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if iValid_p = '1' and ivAddr = cCMD_ADDR then
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if ivData(15 downto 0) = cCMD_RESET then
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sCmdReset <= '1';
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else
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sCmdReset <= '0';
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end if;
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end if;
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if iValid_p = '1' and ivAddr = cCMD_ADDR then
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sCmdValid_syncReg_p <= '1';
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sCmdValid_syncReg_p <= '1';
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else
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else
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sCmdValid_syncReg_p <= '0';
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sCmdValid_syncReg_p <= '0';
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end if;
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end if;
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