| Line 1... |
Line 1... |
##**************************************************************
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##**************************************************************
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## Module : chipscope_vio_console.tcl
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## Module : chipscope_vio_console.tcl
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## Platform : Windows xp sp2
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## Platform : Windows xp sp2
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## Author : Bibo Yang (ash_riple@hotmail.com)
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## Author : Bibo Yang (ash_riple@hotmail.com)
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## Organization : www.opencores.org
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## Organization : www.opencores.org
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## Revision : 2.3
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## Revision : 2.5
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## Date : 2012/11/22
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## Date : 2014/02/08
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## Description : Tcl/Tk GUI for the up_monitor
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## Description : Tcl/Tk GUI for the up_monitor
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##**************************************************************
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##**************************************************************
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############################
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############################
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## include the XILINX procs
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## include the XILINX procs
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| Line 267... |
Line 267... |
set userRegNumber 1
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set userRegNumber 1
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set coreIndex 0
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set coreIndex 0
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set coreRef [list $deviceIndex $userRegNumber $coreIndex]
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set coreRef [list $deviceIndex $userRegNumber $coreIndex]
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csevio_init_core $handle $coreRef
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csevio_init_core $handle $coreRef
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csevio_define_bus $handle $coreRef "usedWord" $CSEVIO_SYNC_INPUT [list 82 83 84 85 86 87 88 89 90 91]
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csevio_define_bus $handle $coreRef "usedWord" $CSEVIO_SYNC_INPUT [list 98 99 100 101 102 103 104 105 106 107]
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csevio_read_values $handle $coreRef inputTclArray
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csevio_read_values $handle $coreRef inputTclArray
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set usedw $inputTclArray(usedWord)
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set usedw $inputTclArray(usedWord)
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csevio_terminate_core $handle $coreRef
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csevio_terminate_core $handle $coreRef
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set tmp 0x
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set tmp 0x
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| Line 306... |
Line 306... |
30 31 32 33 34 35 36 37 38 39\
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30 31 32 33 34 35 36 37 38 39\
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40 41 42 43 44 45 46 47 48 49\
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40 41 42 43 44 45 46 47 48 49\
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50 51 52 53 54 55 56 57 58 59\
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50 51 52 53 54 55 56 57 58 59\
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60 61 62 63 64 65 66 67 68 69\
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60 61 62 63 64 65 66 67 68 69\
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70 71 72 73 74 75 76 77 78 79\
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70 71 72 73 74 75 76 77 78 79\
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80 81]
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80 81 82 83 84 85 86 87 88 89\
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|
90 91 92 93 94 95 96 97]
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csevio_read_values $handle $coreRef inputTclArray
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csevio_read_values $handle $coreRef inputTclArray
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set fifo_data $inputTclArray(fifoContent)
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set fifo_data $inputTclArray(fifoContent)
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csevio_terminate_core $handle $coreRef
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csevio_terminate_core $handle $coreRef
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|
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return $fifo_data
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return $fifo_data
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| Line 354... |
Line 355... |
set userRegNumber 1
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set userRegNumber 1
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set coreIndex 2
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set coreIndex 2
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set coreRef [list $deviceIndex $userRegNumber $coreIndex]
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set coreRef [list $deviceIndex $userRegNumber $coreIndex]
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|
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set trig_leng [string length $trig]
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set trig_leng [string length $trig]
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if {$trig_leng!=14} {
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if {$trig_leng!=18} {
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$log insert end "\nError: Wrong trigger condition length: [expr $trig_leng-2]. Expects: 4+8.\n"
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$log insert end "\nError: Wrong trigger condition length: [expr $trig_leng-2]. Expects: 8+8.\n"
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} else {
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} else {
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if {[format "%d" 0x$pnum]>=511} {
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if {[format "%d" 0x$pnum]>=511} {
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$log insert end "\nError: Wrong trigger pre-capture value: [format "%d" 0x$pnum]. Expects: 0~510.\n"
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$log insert end "\nError: Wrong trigger pre-capture value: [format "%d" 0x$pnum]. Expects: 0~510.\n"
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} else {
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} else {
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csevio_init_core $handle $coreRef
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csevio_init_core $handle $coreRef
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| Line 367... |
Line 368... |
10 11 12 13 14 15 16 17 18 19\
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10 11 12 13 14 15 16 17 18 19\
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20 21 22 23 24 25 26 27 28 29\
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20 21 22 23 24 25 26 27 28 29\
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30 31 32 33 34 35 36 37 38 39\
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30 31 32 33 34 35 36 37 38 39\
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40 41 42 43 44 45 46 47 48 49\
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40 41 42 43 44 45 46 47 48 49\
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50 51 52 53 54 55 56 57 58 59\
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50 51 52 53 54 55 56 57 58 59\
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60 61 62 63 64 65]
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60 61 62 63 64 65 66 67 68 69\
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|
70 71 72 73 74 75 76 77 78 79\
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80 81]
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set outputTclArray(trig) [append pnum $trig]
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set outputTclArray(trig) [append pnum $trig]
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csevio_write_values $handle $coreRef outputTclArray
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csevio_write_values $handle $coreRef outputTclArray
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csevio_terminate_core $handle $coreRef
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csevio_terminate_core $handle $coreRef
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}
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}
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}
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}
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| Line 440... |
Line 443... |
global address_span12
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global address_span12
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global address_span13
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global address_span13
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global address_span14
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global address_span14
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global address_span15
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global address_span15
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global address_span16
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global address_span16
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for {set i 1} {$i<=8} {incr i} {
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for {set i 1} {$i<=8} {set i [expr $i+2]} {
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if {[set address_span$i]==""} {
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if {[set address_span$i]==""} {
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set address_span$i ffff0000
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set address_span$i fffffffc
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}
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}
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}
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}
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for {set i 9} {$i<=16} {incr i} {
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for {set i 2} {$i<=8} {set i [expr $i+2]} {
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if {[set address_span$i]==""} {
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if {[set address_span$i]==""} {
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set address_span$i 00000000
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set address_span$i 00000000
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}
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}
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}
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}
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for {set i 9} {$i<=16} {incr i} {
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if {[set address_span$i]==""} {
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set address_span$i ffffffff
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}
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}
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}
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}
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proc initTrigConfig {} {
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proc initTrigConfig {} {
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global triggerAddr
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global triggerAddr
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global triggerData
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global triggerData
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global triggerPnum
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global triggerPnum
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if {[set triggerAddr]==""} {
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if {[set triggerAddr]==""} {
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set triggerAddr ffff
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set triggerAddr 00000000
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}
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}
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if {[set triggerData]==""} {
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if {[set triggerData]==""} {
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set triggerData a5a5a5a5
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set triggerData a5a5a5a5
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}
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}
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if {[set triggerPnum]==""} {
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if {[set triggerPnum]==""} {
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| Line 520... |
Line 528... |
for {set i 0} {$i<$fifoUsedw} {incr i} {
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for {set i 0} {$i<$fifoUsedw} {incr i} {
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set fifoContent [read_fifo]
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set fifoContent [read_fifo]
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set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2]
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set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2]
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set wr_cptr [expr [format "%d" 0x[string index $fifoContent 0]]%2]
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set wr_cptr [expr [format "%d" 0x[string index $fifoContent 0]]%2]
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set tm_cptr [format "%d" 0x[string range $fifoContent 1 8]]
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set tm_cptr [format "%d" 0x[string range $fifoContent 1 8]]
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set ad_cptr [string range $fifoContent 9 12]
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set ad_cptr [string range $fifoContent 9 16]
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set da_cptr [string range $fifoContent 13 20]
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set da_cptr [string range $fifoContent 17 24]
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if $ok_trig {
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if $ok_trig {
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$log insert end "@@@@@@@@@@@@@@@@@@@@\n"
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$log insert end "@@@@@@@@@@@@@@@@@@@@\n"
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}
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}
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if $wr_cptr {
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if $wr_cptr {
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$log insert end "WR 0x8000$ad_cptr 0x$da_cptr @$tm_cptr\n"
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$log insert end "wr 0x$ad_cptr 0x$da_cptr @$tm_cptr\n"
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} else {
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} else {
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$log insert end "RD 0x8000$ad_cptr 0x$da_cptr @$tm_cptr\n"
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$log insert end "rd 0x$ad_cptr 0x$da_cptr @$tm_cptr\n"
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}
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}
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}
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}
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query_usedw
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query_usedw
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}
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}
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|
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| Line 617... |
Line 625... |
checkbutton .mainframe.f1.address_span_en4 -variable address_span_en4
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checkbutton .mainframe.f1.address_span_en4 -variable address_span_en4
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checkbutton .mainframe.f1.address_span_en5 -variable address_span_en5
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checkbutton .mainframe.f1.address_span_en5 -variable address_span_en5
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checkbutton .mainframe.f1.address_span_en6 -variable address_span_en6
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checkbutton .mainframe.f1.address_span_en6 -variable address_span_en6
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checkbutton .mainframe.f1.address_span_en7 -variable address_span_en7
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checkbutton .mainframe.f1.address_span_en7 -variable address_span_en7
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checkbutton .mainframe.f1.address_span_en8 -variable address_span_en8
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checkbutton .mainframe.f1.address_span_en8 -variable address_span_en8
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label .mainframe.f1.address_span_text1 -text {H:}
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label .mainframe.f1.address_span_text2 -text {L:}
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label .mainframe.f1.address_span_text3 -text {H:}
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label .mainframe.f1.address_span_text4 -text {L:}
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label .mainframe.f1.address_span_text5 -text {H:}
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label .mainframe.f1.address_span_text6 -text {L:}
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label .mainframe.f1.address_span_text7 -text {H:}
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label .mainframe.f1.address_span_text8 -text {L:}
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pack .mainframe.f1.incl_addr \
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pack .mainframe.f1.incl_addr \
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.mainframe.f1.address_span_en1 .mainframe.f1.address_span1 \
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.mainframe.f1.address_span_en1 .mainframe.f1.address_span_text1 .mainframe.f1.address_span1 .mainframe.f1.address_span_text2 .mainframe.f1.address_span2 \
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.mainframe.f1.address_span_en2 .mainframe.f1.address_span2 \
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.mainframe.f1.address_span_en3 .mainframe.f1.address_span_text3 .mainframe.f1.address_span3 .mainframe.f1.address_span_text4 .mainframe.f1.address_span4 \
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.mainframe.f1.address_span_en3 .mainframe.f1.address_span3 \
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.mainframe.f1.address_span_en5 .mainframe.f1.address_span_text5 .mainframe.f1.address_span5 .mainframe.f1.address_span_text6 .mainframe.f1.address_span6 \
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.mainframe.f1.address_span_en4 .mainframe.f1.address_span4 \
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.mainframe.f1.address_span_en7 .mainframe.f1.address_span_text7 .mainframe.f1.address_span7 .mainframe.f1.address_span_text8 .mainframe.f1.address_span8 \
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.mainframe.f1.address_span_en5 .mainframe.f1.address_span5 \
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.mainframe.f1.address_span_en6 .mainframe.f1.address_span6 \
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.mainframe.f1.address_span_en7 .mainframe.f1.address_span7 \
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.mainframe.f1.address_span_en8 .mainframe.f1.address_span8 \
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-side left -ipadx 0
|
-side left -ipadx 0
|
|
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# set the exclusive address entries
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# set the exclusive address entries
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frame .mainframe.f2 -relief groove -borderwidth 5
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frame .mainframe.f2 -relief groove -borderwidth 5
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pack .mainframe.f2
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pack .mainframe.f2
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| Line 648... |
Line 660... |
checkbutton .mainframe.f2.address_span_en12 -variable address_span_en12
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checkbutton .mainframe.f2.address_span_en12 -variable address_span_en12
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checkbutton .mainframe.f2.address_span_en13 -variable address_span_en13
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checkbutton .mainframe.f2.address_span_en13 -variable address_span_en13
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checkbutton .mainframe.f2.address_span_en14 -variable address_span_en14
|
checkbutton .mainframe.f2.address_span_en14 -variable address_span_en14
|
checkbutton .mainframe.f2.address_span_en15 -variable address_span_en15
|
checkbutton .mainframe.f2.address_span_en15 -variable address_span_en15
|
checkbutton .mainframe.f2.address_span_en16 -variable address_span_en16
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checkbutton .mainframe.f2.address_span_en16 -variable address_span_en16
|
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label .mainframe.f2.address_span_text1 -text {H:}
|
|
label .mainframe.f2.address_span_text2 -text {L:}
|
|
label .mainframe.f2.address_span_text3 -text {H:}
|
|
label .mainframe.f2.address_span_text4 -text {L:}
|
|
label .mainframe.f2.address_span_text5 -text {H:}
|
|
label .mainframe.f2.address_span_text6 -text {L:}
|
|
label .mainframe.f2.address_span_text7 -text {H:}
|
|
label .mainframe.f2.address_span_text8 -text {L:}
|
pack .mainframe.f2.excl_addr \
|
pack .mainframe.f2.excl_addr \
|
.mainframe.f2.address_span_en9 .mainframe.f2.address_span9 \
|
.mainframe.f2.address_span_en9 .mainframe.f2.address_span_text1 .mainframe.f2.address_span9 .mainframe.f2.address_span_text2 .mainframe.f2.address_span10 \
|
.mainframe.f2.address_span_en10 .mainframe.f2.address_span10 \
|
.mainframe.f2.address_span_en11 .mainframe.f2.address_span_text3 .mainframe.f2.address_span11 .mainframe.f2.address_span_text4 .mainframe.f2.address_span12 \
|
.mainframe.f2.address_span_en11 .mainframe.f2.address_span11 \
|
.mainframe.f2.address_span_en13 .mainframe.f2.address_span_text5 .mainframe.f2.address_span13 .mainframe.f2.address_span_text6 .mainframe.f2.address_span14 \
|
.mainframe.f2.address_span_en12 .mainframe.f2.address_span12 \
|
.mainframe.f2.address_span_en15 .mainframe.f2.address_span_text7 .mainframe.f2.address_span15 .mainframe.f2.address_span_text8 .mainframe.f2.address_span16 \
|
.mainframe.f2.address_span_en13 .mainframe.f2.address_span13 \
|
|
.mainframe.f2.address_span_en14 .mainframe.f2.address_span14 \
|
|
.mainframe.f2.address_span_en15 .mainframe.f2.address_span15 \
|
|
.mainframe.f2.address_span_en16 .mainframe.f2.address_span16 \
|
|
-side left -ipadx 0
|
-side left -ipadx 0
|
initAddrConfig
|
initAddrConfig
|
|
|
# set the address configuration buttons
|
# set the address configuration buttons
|
frame .mainframe.addr_cnfg -relief groove -borderwidth 5
|
frame .mainframe.addr_cnfg -relief groove -borderwidth 5
|
| Line 673... |
Line 689... |
|
|
# set the transaction trigger controls
|
# set the transaction trigger controls
|
frame .mainframe.trig -relief groove -borderwidth 5
|
frame .mainframe.trig -relief groove -borderwidth 5
|
pack .mainframe.trig
|
pack .mainframe.trig
|
button .mainframe.trig.starttrig -text {Apply Trigger Condition} -command {startTrigger}
|
button .mainframe.trig.starttrig -text {Apply Trigger Condition} -command {startTrigger}
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entry .mainframe.trig.trigvalue_addr -textvar triggerAddr -width 4
|
entry .mainframe.trig.trigvalue_addr -textvar triggerAddr -width 8
|
entry .mainframe.trig.trigvalue_data -textvar triggerData -width 8
|
entry .mainframe.trig.trigvalue_data -textvar triggerData -width 8
|
checkbutton .mainframe.trig.trigaddr -text {@Addr:} -variable trig_aden
|
checkbutton .mainframe.trig.trigaddr -text {@Addr:} -variable trig_aden
|
checkbutton .mainframe.trig.trigdata -text {@Data:} -variable trig_daen
|
checkbutton .mainframe.trig.trigdata -text {@Data:} -variable trig_daen
|
checkbutton .mainframe.trig.wren -text {@WR} -variable trig_wren
|
checkbutton .mainframe.trig.wren -text {@WR} -variable trig_wren
|
checkbutton .mainframe.trig.rden -text {@RD} -variable trig_rden
|
checkbutton .mainframe.trig.rden -text {@RD} -variable trig_rden
|
