URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
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Rev 18 |
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:33:38 JUNE 01, 2009"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:33:38 JUNE 01, 2009"
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set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
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set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
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set_global_assignment -name ENABLE_ADVANCED_IO_TIMING OFF
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set_global_assignment -name ENABLE_ADVANCED_IO_TIMING OFF
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
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set_global_assignment -name VERILOG_FILE vendor.h
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set_global_assignment -name VERILOG_FILE ../../rtl/up_monitor_wrapper.v
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set_global_assignment -name VERILOG_FILE ../../rtl/up_monitor_wrapper.v
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set_global_assignment -name VERILOG_FILE ../../rtl/up_monitor.v
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set_global_assignment -name VERILOG_FILE ../../rtl/up_monitor.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_addr_mask.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_addr_mask.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_trig.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_trig.v
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